IP Library Granted Patent US 8,873,282
Granted Patent B2
US 8,873,282 · App. 13/276,047 · Granted Oct 28, 2014

Interfaces and die packages, and appartuses including the same

Inventor: Oh Seung Min (Icheon-si, KR)
Assignee: Micron Technology, Inc.
G11C7/10H01L2225/0651H01L2224/32145H01L2224/49175H01L2224/48227G11C7/1093H01L2224/06155H01L2224/73265H01L23/48H01L2224/48147H01L2225/06562G11C7/1012H01L2224/32225H01L2224/48145H01L25/18G11C7/1069H01L24/48H01L2224/04042H01L2225/06506G11C7/1066H01L2924/15192
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Quick Facts
Patent No.
US 8,873,282
App. No.
13/276,047
Granted
Oct 28, 2014
Kind
B2
Abstract

A memory device includes a die package including a plurality of memory dies, an interface including an interface circuit, and a memory controller to control the interface with control data received from at least one die. The interface is to divide and multiplex an IO channel between the package and the controller into more than one channel using the data received from the at least one die. The interface includes a control input buffer to receive an enable signal through a control pad, a first input buffer to receive first data through a first IO pad in response to a first state of the enable signal, and a second input buffer to receive second data through a second IO pad in response to a second state of the enable signal. The interface further includes an input multiplexer to multiplex the first data and the second data to provide input data.

Claims (11)

1. An apparatus, comprising:

a die package including a plurality of groups of circuits, each of the plurality of groups of circuits including a plurality of dice; and

an interface configured to intervene a channel between a controller and the plurality of groups of circuits and configured to divide the channel between the die package and the controller into a number of channels with at least one channel corresponding to each circuit of the plurality of groups of circuits, the interface being couplable to a selected one of the plurality of groups of circuits through an associated one of the number of channels in response to an external control signal with the interface being coupled to only one plurality of groups of circuits at a time.

2. The apparatus of claim 1 , wherein the die package comprises a memory die package, the controller comprises a memory controller, and the plurality of dice comprises a plurality of memory dice.

3. The apparatus of claim 1 , wherein each of the plurality of dice are grouped within only one of the plurality of groups of circuits and each of the number of channels is selectively coupled with the controller, a selected one of the plurality of dice within the only one of the plurality of circuits being coupled to the controller through a chip enable signal to be provided from the interface to the selected one of the plurality of dice.

4. The apparatus of claim 1 , wherein each of the number of channels comprises at least one type of interconnect selected from interconnects including a wire, a trace, a direct connection between the controller and a respective group of the plurality of circuits.

5. The apparatus of claim 1 , wherein the interface is further configured to divide the channel into a plurality of input/output (IO) channels.

6. The apparatus of claim 5 , wherein one of the plurality of IO channels is coupled between a first IO pad of the controller and IO pads on each of a first group of the plurality of dice that are disposed in a first portion of the die package, and another one of the plurality of IO channels is coupled between a second IO pad of the controller and IO pads on each of a second group of the plurality of dice that are disposed in a second portion of the die package.

7. An apparatus, comprising:

a die package including a plurality of groups with each group including a unique plurality of dice, each of the plurality of groups having at least one channel; and

an interface configured to intervene between the at least one channel of each of the plurality of groups and a controller, the interface being further configured to select the at least one channel from a selected one of the plurality of groups and to multiplex the selected at least one channel into a single channel to couple to the controller in response to a control signal received from at least one of the plurality of dice, the interface being couplable between only one of the at least one channel and the controller at a time.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2013
From: MIN, OH SEUNG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030873/0708 →
Continuity (1)
Related Publication 20130094301A1 · Apr 18, 2013