Metal gate structure of a semiconductor device
The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.
1. A complementary metal-oxide-semiconductor (CMOS) semiconductor device comprising:
a substrate comprising an isolation region adjacent to and separating a P-active region and an N-active region;
a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and
an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.
2. The CMOS semiconductor device of claim 1 further comprising an oxygen-containing TaN layer between the oxygen-containing TiN layer and the P-work function metal.
3. The CMOS semiconductor device of claim 1 further comprising a nitrogen-rich TaN layer between the nitrogen-rich TiN layer and the N-work function metal.
4. The CMOS semiconductor device of claim 1 further comprising a nitrogen-containing gate dielectric layer between the nitrogen-rich TiN layer and substrate.
5. The CMOS semiconductor device of claim 1 , wherein the N-metal gate electrode has a recess and P-metal gate electrode has a protrusion extending into the recess.
6. The CMOS semiconductor device of claim 1 , wherein a ratio of a maximum width of the P-metal gate electrode to a minimum width of the N-metal gate electrode is from about 1.05 to 1.2.
7. The CMOS semiconductor device of claim 1 further comprising an oxygen-containing TaN layer between the N-work function metal and the P-work function metal.
8. The CMOS semiconductor device of claim 1 further comprising a nitrogen-rich TaN layer between the N-work function metal and the P-work function metal.
9. The CMOS semiconductor device of claim 1 , wherein the N-work-function metal comprises a metal selected from a group of Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr.
10. The CMOS semiconductor device of claim 1 , wherein the P-work-function metal comprises a metal selected from a group of TiN, WN, TaN, and Ru.
11. A complementary metal-oxide-semiconductor (CMOS) semiconductor device comprising:
a substrate comprising an isolation region separating a P-active region and an N-active region;
a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and a doped TiN layer between the P-work function metal and substrate; and
an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer contacts the doped TiN layer over the isolation region.
12. The CMOS semiconductor device of claim 11 , wherein the doped TiN layer comprises an oxygen-containing TiN layer or a fluorine-containing TiN layer.
13. The CMOS semiconductor device of claim 11 , wherein a ratio of a width of the P-metal gate to a width of the N-metal gate ranges from about 0.8 to about 1.2.
14. The CMOS semiconductor device of claim 11 , wherein the P-metal gate comprises a signal metal over the P-work function metal.
15. The CMOS semiconductor device of claim 11 , wherein the N-metal gate comprises a signal metal over the N-work function metal.
16. The CMOS semiconductor device of claim 11 , further comprising a high-k dielectric layer between the doped TiN layer and the substrate and between the nitrogen-rich TiN layer and the substrate.
17. The CMOS semiconductor device of claim 11 , wherein the P-metal gate comprises a P-barrier layer between the P-work function metal and the doped TiN layer.
18. The CMOS semiconductor device of claim 11 , wherein the N-metal gate comprises an N-barrier layer between the N-work function metal and the nitrogen-rich TiN layer.
19. A complementary metal-oxide-semiconductor (CMOS) semiconductor device comprising:
a substrate comprising an isolation region separating a P-active region and an N-active region; and
a gate structure over the substrate, the gate structure comprises:
a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and a doped TiN layer between the P-work function metal and substrate;
an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer contacts the doped TiN layer over the isolation region; and
a TaN layer between the P-metal gate electrode and the N-metal gate electrode.
20. The CMOS semiconductor device of claim 19 , wherein the TaN layer comprises a nitrogen-rich TaN layer, an oxygen-containing TaN layer or a fluorine-containing TaN layer.