IP Library Granted Patent US 8,518,764
Granted Patent B2
US 8,518,764 · App. 13/279,776 · Granted Aug 27, 2013

Semiconductor structure having a through substrate via (TSV) and method for forming

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Quick Facts
Patent No.
US 8,518,764
App. No.
13/279,776
Granted
Aug 27, 2013
Kind
B2
Abstract

A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.

Claims (40)

1. A method of forming a semiconductor device structure using a semiconductor substrate having a background doping of a first concentration and of a first conductivity type, comprising:

forming a device in and on a first side of the semiconductor substrate having a first doped region of a second conductivity type, wherein the second doped region has a first depth below the first side;

forming an opening through the substrate extending between the first side and a second side of the substrate;

forming a second doped region, wherein the second doped region is in the opening extending to a second depth from the first side greater than the first depth, has a second concentration greater than the first concentration, and is of the first conductivity type; and

filling the opening with metal, wherein the metal is in contact with the second doped region.

2. The method of claim 1 , wherein the forming the second doped region comprises depositing in-situ doped polysilicon in the opening.

3. The method of claim 1 , wherein the forming the second doped region comprises performing an implant to apply dopant to a sidewall of the opening to the second depth.

4. The method of claim 3 , wherein the forming a device comprises forming one of a group consisting of a laterally diffused MOS (LDMOS) transistor having a drift region as the first doped region and a ring on the first side around the opening, wherein the ring is the first doped region.

5. A semiconductor device structure including a substrate having a background doping of a first concentration and of a first conductivity type, comprising:

a through substrate via (TSV) through the substrate;

a device on a first side of the substrate, wherein the device has a first doped region of a second conductivity type;

a second doped region around the TSV, wherein the second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type,

wherein the device is a laterally diffused MOS (LDMOS) transistor coupled to the TSV, wherein the LDMOS transistor has a body connection of the first conductivity type coupled to the TSV, and wherein the second doped region extends to a depth in the substrate below a depth of the body connection.

6. The semiconductor device structure of claim 5 , wherein the first doped region is source of the LDMOS transistor adjacent to the body connection.

7. The semiconductor device structure of claim 6 , wherein the LDMOS transistor has a gate and the source is aligned to one side of the gate.

8. The semiconductor device structure of claim 5 wherein the second doped region directly contacts the TSV.

9. The semiconductor device structure of claim 5 , wherein the first doped region encircles the TSV.

10. A semiconductor device structure including a substrate having a background doping of a first concentration and of a first conductivity type, comprising:

a through substrate via (TSV) through the substrate;

a device on a first side of the substrate, wherein the device has a first doped region of a second conductivity type;

a second doped region around the TSV, wherein the second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type,

wherein the first doped region comprises a drift region of the LDMOS transistor extending to a first depth below the first side of the substrate, the second doped region extends to a second depth below the first side of the substrate, the second depth is greater than the first depth, and wherein the second depth is not less than ten times greater than the first depth.

11. A semiconductor device structure including a substrate having a background doping of a first concentration and of a first conductivity type, comprising:

a through substrate via (TSV) through the substrate;

a device on a first side of the substrate, wherein the device has a first doped region of a second conductivity type;

a second doped region around the TSV, wherein the second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type, wherein the second concentration exceeds the first concentration by more than ten thousand times, and wherein the LDMOS transistor has a drift region extending to a first depth below the first side of the substrate, the doped region extends to a second depth below the first side of the substrate, and the second depth is greater than the first depth by at least a factor of 5.

12. A semiconductor device structure, comprising:

a semiconductor substrate having a via through the semiconductor substrate from a first side to a second side;

a device on a first side having a first doped region;

a second doped region around and in contact with the via; and

wherein:

the substrate has a background doping level of a first concentration;

the substrate has a first conductivity type;

the first doped region is of the second conductivity type and has a first depth below the substrate;

the second doped region has a second depth below the substrate;

the second depth is greater than the first depth;

the second doped region has a doping level of a second concentration; and

the second concentration is greater than the first concentration.

13. The semiconductor device structure of claim 12 , wherein the first doped region comprises a drift region of an LDMOS device.

14. The semiconductor device structure of claim 12 , wherein the first doped region encircles the second doped region.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0379 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0447 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0439 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027821/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2011
From: DAO, THUY B.; KEYS, JOEL E.; RUEDA, HERNAN A.; SANDERS, PAUL W.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 027110/0029 →