Router and switch architecture

1. A packet switching system for a packet transfer network comprising:

a plurality of line cards, each line card comprising an ingress path pipeline and an egress buffer; and

an electro-optical In/Out (IO) interconnect coupling the ingress path pipeline of each line card to the egress buffer of the other line cards, wherein said electro-optical IO interconnect includes:

a CMOS chip with logic circuitry coupled to a matrix of vertical-cavity surface-emitting lasers (VCSELs) and to a matrix of Photo Detectors (PDs), and

interface circuitry between the logic circuitry on said CMOS chip and said matrix of VCSELs, and between the logic circuitry on said CMOS chip and said PDs;

wherein the ingress path pipeline of each line card is configured to:

i) receive a packet from the packet transfer network,

ii) perform ingress processing on the received packet,

iii) perform partial egress processing on the received packet, including classifying and identifying the egress destination address,

iv) attach data to the received packet identifying any additional egress processing still required for the packet, and

v) send the processed packet to the egress buffer of another line card using the electro-optical IO interconnect.

2. The packet switching system according to claim 1 , wherein said electro-optical IO interconnect further includes:

a first matrix of passive optical elements coupled to said matrix of VCSELs; and

a second matrix of passive optical elements coupled to said matrix of PDs;

wherein said PD and VCSEL matrixes are mechanically and thermally isolated from the first and second matrixes of passive optical elements.

3. The packet switching system according to claim 1 , wherein said electro-optical IO interconnect includes a congestion-free path from the ingress path pipeline of each line card to the egress buffer of each line card regardless of the type of traffic arriving at the line cards from the packet transfer network.

4. A method of creating a packet switching system for a packet transfer network comprising:

providing a plurality of line cards, each line card comprising an ingress path pipeline and an egress buffer;

coupling the ingress path pipeline of each line card to the egress buffer of the other line cards by an electro-optical In/Out (IO) interconnect, wherein said electro-optical IO interconnect includes:

a CMOS chip with logic circuitry coupled to a matrix of vertical-cavity surface-emitting lasers (VCSELs) and to a matrix of Photo Detectors (PDs), and

interface circuitry between the logic circuitry on said CMOS chip and said matrix of VCSELs, and between the logic circuitry on said CMOS chip and said PDs;

receiving a packet at the ingress path pipeline of a first line card of the plurality of line cards from the packet transfer network;

performing at the ingress path pipeline of the first line card ingress processing and partial egress processing on the received packet, the partial egress processing including classifying and identifying the egress destination address,

attaching data to the received packet identifying any additional egress processing still required for the packet; and

sending the processed packet to the egress buffer of another line card using the electro-optical IO interconnect.

5. The method according to claim 4 , further comprising:

coupling a first matrix of passive optical elements to said matrix of VCSELs; and

coupling a second matrix of passive optical elements to said matrix of PDs;

wherein the PD and VCSEL matrixes are mechanically and thermally isolated from the first and second matrixes of passive optical elements.

6. A method of packet switching through a packet switching network comprising:

receiving a packet in an ingress path pipeline in a first line card;

performing ingress processing and partial egress processing on the received packet in said ingress path pipeline, the partial egress processing including classifying and identifying a destination address of said packet;

attaching data to the received packet identifying additional egress processing still required for the packet;

transferring said processed packet to an egress buffer on a second line card via an electro-optical In/Out (IO) interconnect, wherein the electro-optical IO interconnect includes:

a CMOS chip with logic circuitry coupled to a matrix of vertical-cavity surface-emitting lasers (VCSELs) and to a matrix of Photo Detectors (PDs), and

interface circuitry between the logic circuitry on said CMOS chip and said matrix of VCSELs, and between the logic circuitry on said CMOS chip and said PDs; and

performing said additional egress processing in said egress buffer.

7. The method according to claim 6 , wherein said step of transferring is performed at a speed up of an integer number.

8. The method according to claim 7 , wherein the integer number is equal to a total number of line cards in a packet switching system.

9. The method according to claim 6 , wherein said ingress processing includes light modulation.

10. The method according to claim 6 , wherein said egress buffer receives packets from a plurality of ingress pipelines simultaneously.

11. The method according to claim 6 , wherein said egress buffer is configured to receive packets from all ingress pipelines in a packet switching system simultaneously.

12. The method according to claim 6 , further comprising transferring said packet over a permanent congestion-free path through said electro-optical IO interconnect to said egress buffer after said partial egress processing.