Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.
1. An integrated circuit comprising:
a plurality of word lines;
a plurality of conductive plugs comprising, as seen in plan view:
blocks of conductive material with a non-rectangular, parallelogram footprint, flanked on first and second opposite sides by two of the word lines, and flanked on second and third opposite sides by blocks of insulating material,
a plurality of bit lines overlying the conductive plugs; and
a plurality of active areas underlying the conductive plugs;
wherein each of the blocks of conductive material are configured to contact at least one of the underlying active areas and provide an electrical connection with at least one of the overlying bit lines.
2. The integrated circuit of claim 1 , wherein the non-rectangular, parallelogram footprint is a rhomboid footprint.
3. The integrated circuit of claim 2 , wherein the non-rectangular, parallelogram footprint has at least two interior angles of between approximately 20 and approximately 30 degrees.
4. The integrated circuit of claim 2 , wherein the non-rectangular, parallelogram footprint has at least two interior angles of between approximately 40 and approximately 50 degrees.
5. The integrated circuit of claim 1 , wherein the overlying bit lines each have a zig-zag configuration.
6. The integrated circuit of claim 5 , wherein the zig-zag configuration has two slopes that intersect at an angle in a range of between 45 and 179 degrees.
7. The integrated circuit of claim 6 , wherein the angle is about 130 degrees.
8. The integrated circuit of claim 1 , wherein the blocks of conductive material are associated with a plan view pattern, the pattern comprising:
first columns, each first column comprising one of the word lines;
second columns alternating regularly with the first columns, each second column comprising the blocks of conductive material, which alternate up and down each of the second columns with the blocks of insulating material, the second columns arranged in ascending and descending trios, wherein:
the ascending trios each comprise three sequential second columns having blocks of conductive material with parallelogram footprints, each parallelogram footprint having a top edge parallel to a bottom edge, wherein the top and bottom edges of the parallelogram slope upwardly to the right, and each top edge is aligned with the top edge of two other blocks of conductive material in other second columns in the ascending trios; and
the descending trios each comprise three sequential second columns having blocks of conductive material with parallelogram footprints, each parallelogram footprint having a top edge parallel to a bottom edge, wherein the top and bottom edges of the parallelogram slope downwardly to the right, and each top edge is aligned with the top edge of two other blocks of conductive material in other second columns in the descending trios.
9. The integrated circuit of claim 8 , wherein the slope of the top and bottom edges of the parallelogram footprints in the ascending trios intersects with the slope of the top and bottom edges of the parallelogram footprints in the descending trios at an angle in the range of between 45 and 179 degrees.
10. The integrated circuit of claim 9 , wherein the angle is about 130 degrees.
11. The integrated circuit of claim 8 wherein:
each of the overlying bit lines have a zig-zag configuration;
each of the overlying bit lines have two slopes that intersect at an angle in a range of between 45 and 179 degrees; and
each of the overlying bit lines cross over the active areas.
12. The integrated circuit of claim 1 , wherein the underlying active areas are oval shaped.
13. The integrated circuit of claim 12 , wherein the underlying active areas comprise one source region and two drain regions, and both word lines contact the source region.
14. An integrated circuit, comprising a component grouping comprising, as seen in plan view:
an elongate active area comprising:
a source;
a first drain; and
a second drain on a side of the source opposite the first drain, wherein the active area is elongated along an axis;
a first word line positioned at least partially between the first drain and the source;
a second word line positioned at least partially between the second drain and the source;
a plurality of conductive contact plugs having a rhomboid shape,
wherein the plurality of contact plugs contact and generally overlie the active area, and wherein at least one of the plurality of contact plugs extends between the first word line and the second word line, the plurality of contact plugs being substantially parallel with the axis defined by the active area.
15. The memory device of claim 14 , wherein the active areas are oval shaped.
16. The memory device of claim 15 , wherein some contact plugs extend beyond the oval boundary of the active area.
17. The memory device of claim 14 , wherein each of the rhomboid portions of conductive material has at least two interior angles of between approximately 20 and approximately 30 degrees.
18. The memory device of claim 14 , wherein the rhomboid portions of conductive material have at least two interior angles of between approximately 40 and approximately 50 degrees.
19. The memory device of claim 14 , further comprising an overlying bit line electrically connected with at least some of the rhomboid portions of conductive material.
20. The memory device of claim 19 , wherein the overlying bit line intersects with and is non-perpendicular to the axis at the points of intersection.
21. The memory device of claim 20 , wherein the first and second word lines intersect with and are non-perpendicular to the axis at the points of intersection.