Semiconductor device

1. A semiconductor device, comprising:

a substrate having a transistor region and a resistor region;

a shallow trench isolation (STI) on the resistor region of the substrate;

a tank in the STI; and

a resistor in the tank and on a horizontal top surface of the STI surrounding the tank.

2. The semiconductor device of claim 1 , wherein the resistor comprises a polysilicon layer in the tank and two contacts on the STI adjacent to two sides of the tank.

3. The semiconductor device of claim 2 , further comprising a contact etch stop layer (CESL) on part of the substrate and the polysilicon layer.

4. The semiconductor device of claim 3 , further comprising a metal gate on the transistor region, wherein the top of the metal gate is even with the surface of the CESL.

5. The semiconductor device of claim 4 , further comprising:

a first dielectric layer on the substrate and the CESL;

a passivation layer on the metal gate, the first dielectric layer, and the CESL;

a second dielectric layer on the passivation layer; and

a plurality of contact plugs in the second dielectric layer, the passivation layer, and the first dielectric layer for connecting the metal gate and the contacts.

6. The semiconductor device of claim 5 , wherein the passivation layer comprises SiCN or the oxide of the gate.

7. The semiconductor device of claim 2 , wherein at least part of the polysilicon layer comprises a dopant.

8. The semiconductor device of claim 7 , wherein the dopant comprises boron atoms.

9. The semiconductor device of claim 2 , wherein each of the contacts comprises an interfacial layer, a high-k dielectric layer, a barrier layer, a work function metal layer, and a conductive layer.

10. The semiconductor device of claim 9 , wherein the high-k dielectric layer is U-shaped or I-shaped.

11. The semiconductor device of claim 9 , wherein the work function metal layer is U-shaped.