Method of manufacturing semiconductor device

1. A method of manufacturing a semiconductor device comprising a capacitor region on which at least a capacitor is formed and a non-capacitor region on which no capacitor is formed, wherein the method comprises:

prescribing the capacitor region and the non-capacitor region by forming a capacitor at a first height on a semiconductor substrate of which the surface is substantially flat;

covering the non-capacitor region and the capacitor with an interlayer insulating film with a thickness that is greater than the height of the capacitor, the interlayer insulating film comprising first, second and third portions, the first portion being over the non-capacitor region and including a substantially even surface at a second height greater than the first height, a second portion being over the capacitor and including a substantially even surface at a third height greater than the second height, and the third portion intervening between the first and second portions and including a slant surface to interface the substantially even surface of the first portion with the substantially even surface of the second portion;

performing a selective etching on the second portion of the interlayer insulating film to leave first and second parts thereof, the first part being over a major part of the capacitor and including a substantially even surface at a fourth height greater than the first height and less than the third height, and the second part being over a remaining part of the capacitor to intervene between the first part and the third portion of the interlayer insulating film and including a substantially even surface at the third height and a side surface interfacing the substantially even surfaces of the first and second parts with each other; and

performing a chemical mechanical polishing to remove the third portion and the second part of the interlayer insulating film so that the interlayer insulating film is flattened to provide an insulating layer covering both the non-capacitor region and the capacitor in a substantially even height greater than the first height,

wherein the selective etching on the second portion of the interlayer insulating film is performed to make a difference H d between the third and fourth heights and a distance Lr of a sum of the third portion and the second part in a horizontal direction along the surface of the semiconductor substrate satisfy an aspect ratio (H d /Lr) of the H d to the Lr being equal to or less than 0.6 so that the third portion and the second part are removed by the chemical mechanical polishing while preventing the third portion and the second part from peeling off from the interlayer insulating film.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein the aspect ratio (H d /Lr) is equal to or less than 0.25.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein the fourth height is substantially the same as the second height.

4. The method of manufacturing a semiconductor device according to claim 1 , wherein the Lr is equal to or more than four times the first height.

5. The method of manufacturing a semiconductor device according to claim 1 , wherein the Lr is equal to or less than 10 μm.

6. The method of manufacturing a semiconductor device according to claim 1 , wherein the chemical mechanical polishing method comprises pushing a surface of the semiconductor substrate against a polishing pad with a first pressure, and increasing the pressure to a second pressure that is higher than the first pressure.

7. The method of manufacturing a semiconductor device according to claim 6 , wherein the first pressure is equal to or less than 2 psi.

8. The method of manufacturing a semiconductor device according to claim 1 , wherein the chemical mechanical polishing method comprises making a surface of the semiconductor substrate and a polishing pad be in contact with each other with a first relative speed, and increasing the speed to a second relative speed that is higher than the first relative speed.

9. The method of manufacturing a semiconductor device according to claim 8 , wherein the first relative speed is equal to or lower than 0.19 m/sec.

10. The method of manufacturing a semiconductor device according to claim 8 , wherein acceleration when the speed is increased from the first relative speed to the second relative speed is equal to or lower than 0.19 m/sec 2 .

11. The method of manufacturing a semiconductor device according to claim 10 , wherein the making the surface of the semiconductor device and the polishing pad be in contact with each other with the first relative speed is performed with a rotating speed of the polishing pad of 10 rpm or less and with a rotating speed of the semiconductor substrate of 10 rpm or less.

12. The method of manufacturing a semiconductor device according to claim 11 , wherein the increasing to the second relative speed is performed with rotating acceleration of 10 rpm/sec or less.

13. The method of manufacturing a semiconductor device according to claim 1 , wherein the interlayer insulation film is a two-layer laminated film.

14. The method of manufacturing a semiconductor device according to claim 13 , wherein in the laminated film, a step coverage of a lower-layer film is more superior to a step coverage of an upper-layer film.

15. The method of manufacturing a semiconductor device according to claim 1 , wherein the capacitor comprises a capacitive dielectric film that covers inner and outer walls of a cup-shaped lower electrode and an upper electrode that covers the capacitive dielectric film, and an upper surface of the upper electrode forms a plate electrode that is substantially flat in the horizontal direction.

16. The method of manufacturing a semiconductor device according to claim 15 , wherein the capacitor comprises a support film that supports the lower electrode near an upper end of the lower electrode, and the capacitive dielectric film and the upper electrode cover the support film.

17. The method of manufacturing a semiconductor device according to claim 16 , wherein the upper electrode of the capacitor region has an outer edge that is substantially rectangular as seen from a plane, and an outer edge of the projected portion that is prescribed as the rising point of the interlayer insulating film has a substantially rectangular outer circumference that follows the outer edge of the upper electrode of the capacitor region.