IP Library Granted Patent US 8,753,948
Granted Patent B2
US 8,753,948 · App. 13/285,557 · Granted Jun 17, 2014

Methods of forming laterally diffused metal oxide semiconductor transistors for radio frequency power amplifiers

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Quick Facts
Patent No.
US 8,753,948
App. No.
13/285,557
Granted
Jun 17, 2014
Kind
B2
Abstract

A lateral diffused metal oxide semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. A method for forming the LDMOS transistor is also provided.

Claims (41)

1. A method for forming a lateral diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:

providing a substrate having a first surface and a second surface, wherein the first surface comprises an epitaxial layer, and wherein the first surface comprises a drain region, a source region, and a channel region for the LDMOS transistor;

implanting a first dopant of a first type having a first doping concentration in the first surface of the substrate, wherein the first dopant is implanted to a first depth, and wherein the first dopant is implanted in the source region, the drain region, and the channel region;

forming a gate electrode over the channel region of the first surface of the substrate;

selectively implanting a second dopant of a second type in the source region of the first surface, the second dopant having a second doping concentration, wherein the second dopant laterally diffusing under the gate electrode a predetermined distance, and wherein the second type is different than the first type;

selectively implanting a third dopant of the first type in the drain region of the first surface, the third dopant having a third doping concentration, wherein the third dopant is implanted to a second depth, the second depth being less than the first depth;

forming a source implant in the source region; and

forming a drain implant in the drain region.

2. The method of claim 1 , further comprising forming a sinker implant in the source region, wherein the sinker implant is used to provide a connection from the source region to the second surface of the substrate.

3. The method of claim 1 , wherein the first type is an N-type dopant and the second type is a P-type dopant.

4. The method of claim 1 , wherein the gate electrode is formed from polysilicon.

5. The method of claim 1 , wherein the epitaxial layer is lightly doped relative to a doping concentration of the substrate.

6. The method of claim 1 , wherein selectively implanting the second dopant further comprises laterally diffusing the second dopant for substantially an entire length of the gate electrode.

7. The method of claim 1 , wherein forming the source implant and forming the drain implant comprise forming an N+ source implant and forming an N+ drain implant.

8. The method of claim 1 , wherein selectively implanting the third dopant further comprises implanting the third dopant with no lateral diffusion under the gate electrode.

9. The method of claim 1 , wherein the first dopant is implanted before the gate electrode is formed.

10. The method of claim 1 , wherein a net doping concentration of the drain region is greater than either of the first doping concentration or the third doping concentration.

11. A method for forming a lateral diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:

providing a substrate having a first surface and a second surface, wherein the first surface comprises an epitaxial layer, and wherein the first surface comprises a drain region, a source region, and a channel region for the LDMOS transistor;

implanting a first N-type dopant having a first doping concentration in the first surface of the substrate, wherein the first N-type dopant is implanted to a first depth, and wherein the first N-type dopant is implanted in the source region, the channel region, and the drain region;

forming a gate electrode over the channel region of the first surface of the substrate;

selectively implanting a P-type dopant in the source region of the first surface, the P-type dopant having a second doping concentration, wherein the P-type dopant laterally diffusing under the gate electrode into the channel region a predetermined distance;

selectively implanting a second N-type dopant in the drain region of the first surface, the second N-type dopant having a third doping concentration, wherein the second N-type dopant is implanted to a second depth, the second depth being less than the first depth;

forming an N+ source implant in the source region; and

forming an N+ drain implant in the drain region.

12. The method of claim 11 , further comprising forming a sinker implant in the source region, wherein the sinker implant is used to provide a connection from the source region to the second surface of the substrate.

13. The method of claim 11 , wherein the gate electrode is formed from polysilicon.

14. The method of claim 11 , wherein the epitaxial layer is lightly doped relative to a doping concentration of the substrate.

15. The method of claim 11 , wherein selectively implanting the second dopant further comprises laterally diffusing the second dopant for substantially an entire length of the gate electrode.

16. The method of claim 11 , wherein selectively implanting the third dopant further comprises implanting the third dopant with minimal lateral diffusion under the gate electrode.

17. A method for forming a lateral diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:

forming a first implant of a first type and a first doping density to a first depth in a substrate having a source region, a drain region, and a channel region, wherein the first implant is formed in at least the drain region and the channel region;

forming a gate electrode over the channel region;

after forming the gate electrode, forming a second implant of a second type that is different from the first type in the source region of the substrate, the second implant laterally diffused under the gate electrode into the channel region a predetermined distance, wherein the second implant overlaps a portion of the first implant within the channel region; and

forming a third implant of the first type and a second doping density that is greater than the first doping density to a second depth in the drain region of the substrate, the second depth being less than the first depth.

18. The method of claim 17 , further comprising:

forming an N+ source implant in the source region a first predetermined distance from the gate electrode; and

forming an N+ drain implant in the drain region a second predetermined distance from the gate electrode,

wherein the third implant is formed in the channel region from an edge of the gate electrode to the N+ drain implant.

19. The method of claim 17 , wherein the second implant is laterally diffused under the gate electrode for substantially an entire length of the gate electrode.

20. The method of claim 17 , wherein the first implant and the third implant each comprises an N-type dopant, and the second implant comprises a P-type dopant.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
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To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
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To: NXP B.V.
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To: NXP USA, INC.
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MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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To: NXP B.V.
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To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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