Power and ground routing of integrated circuit devices with improved IR drop and chip performance
An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.
1. An integrated circuit chip comprising:
a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper;
a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers;
at least a first power/ground mesh wiring line in a first aluminum layer overlying said first Insulating layer, for distributing power signal or ground signal; and
at least a second power/ground mesh wiring line in a second aluminum layer overlying said first aluminum layer, for distributing power signal or ground signal.
2. The integrated circuit chip of claim 1 further comprising a second insulating layer covering said first aluminum layer and said first insulating layer.
3. The integrated circuit chip of claim 2 further comprising a third insulating layer covering said second aluminum layer and said second insulating layer.
4. The integrated circuit chip of claim 3 , wherein the third insulating layer is a passivation layer.
5. The integrated circuit chip of claim 1 further comprising a bonding area and an aluminum pad on the second insulating layer within the bonding area.
6. The integrated circuit chip of claim 2 further comprising a third insulating layer covering said second power/ground mesh wiring line.