IP Library Granted Patent US 8,330,540
Granted Patent B2
US 8,330,540 · App. 13/288,741 · Granted Dec 11, 2012

Model based distortion reduction for power amplifiers

Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 8,330,540
App. No.
13/288,741
Filed
Nov 3, 2011
Granted
Dec 11, 2012
Kind
B2
Art Unit
2817
USPC
330/149
Abstract

A method of processing a signal is disclosed. The method comprises generating a digital signal, converting the digital signal to an analog signal, and generating an amplified analog signal having distortions. The method further comprises converting the amplified analog signal to a feedback digital signal at a sample rate and updating a model of the distortions based on the feedback digital signal.

Claims (60)

1. A method of processing a digital signal, comprising:

converting the digital signal to an analog signal at a first rate;

amplifying the analog signal to generate an amplified analog signal having distortions;

converting the amplified analog signal to a feedback digital signal;

determining a difference between the digital signal and the feedback digital signal to provide an error signal;

updating a model of the distortions to minimize the error signal at a second rate, the second rate being less than the first rate; and

estimating the distortions within the digital signal using the model.

2. The method of claim 1 , wherein the step of updating comprises:

updating one or more coefficients of a piecewise linear filter to update the model.

3. The method of claim 1 , wherein the step of updating comprises:

updating memory effects within the model of the distortions.

4. The method of claim 1 , wherein the step of updating comprises:

updating one or more coefficients of a finite impulse response filter to update the model.

5. The method of claim 1 , wherein the step of updating comprises:

updating one or more coefficients of an infinite impulse response filter.

6. The method of claim 1 , wherein the step of updating comprises:

updating the model at the second rate, the second rate being a selectable rate that is less than the first rate.

7. The method of claim 1 , wherein step of updating comprises:

adapting the model based on the error signal.

8. The method of claim 1 , wherein step of updating comprises:

adapting the model based on a second error signal derived from a difference between the digital signal and the feedback digital signal.

9. The method of claim 1 , further comprising:

pre-compensating for the distortions by removing the estimate of the distortions from the digital signal.

10. The method of claim 1 , further comprising:

subtracting the estimate of the distortions from the digital signal to create a precompensated digital signal; and

converting the precompensated digital signal to the analog representation of the digital signal.

11. The method of claim 1 , wherein the step of updating comprises:

updating the model such that the distortions in the amplified analog signal are reduced for frequencies higher than half the first rate.

12. The method of claim 10 , wherein the step of updating comprises:

adapting the model based on a second error signal derived from the precompensated digital signal and the feedback digital signal.

13. The method of claim 10 , wherein the step of updating comprises:

adapting the model based on a second error signal derived from a difference between the feedback digital signal and a sum of the precompensated digital signal and the estimate of the distortions.

14. The method of claim 10 , wherein the step of updating comprises:

adapting the model based on a second error signal derived from a difference between the estimate of the distortions and a difference between the feedback digital signal and the precompensated digital signal.

15. A system for processing a digital signal comprising:

a first converter configured to convert the digital signal to an analog signal at a first rate;

an amplifier configured to amplify an analog representation of the digital signal to generate an amplified analog signal having distortions;

a second converter configured to convert the amplified analog signal to a feedback digital signal;

an error calculator configured to determine a difference between the digital signal and the feedback digital signal to provide an error signal;

a model adaptor configured to update a model of the distortions to minimize the error signal at a second rate, the second rate being less than the first rate; and

a model module configured to estimate the distortions within the digital signal using the model.

16. The system of claim 15 , wherein the model module comprises:

a piecewise-linear filter.

17. A system as in The system of claim 15 , wherein the model includes memory effects.

18. The system of claim 15 , wherein the model module comprises:

a finite impulse response filter.

19. The system of claim 15 , wherein the model module comprises:

an infinite impulse response filter.

20. The system of claim 15 , wherein the second rate, is a selectable rate that is less than the first rate.

21. The system of claim 15 , wherein the model adaptor is configured to update the model based on the error signal.

22. The system of claim 15 , wherein the model adaptor is configured to update the model based on a second error signal derived from a difference between the digital signal and the feedback digital signal.

23. The system of claim 15 , further comprising:

a summation node configured to remove the estimate of the distortions from the digital signal to pre-compensate for the distortions.

24. The system of claim 15 , further comprising:

a summation node configured to subtract the estimate of the distortions from the digital signal to create a precompensated digital signal,

wherein the amplifier is configured to amplify the precompensated digital signal to generate the amplified analog signal.

25. The system of claim 15 , wherein the model is configurable to reduce distortions in the amplified analog signal for frequencies higher than half the sample rate of the feedback digital signal.

26. The system of claim 24 , wherein the model adaptor is configured to update the model based on a second error signal derived from the precompensated digital signal and the feedback digital signal.

27. The system of claim 24 , wherein the model adaptor is configured to update the model based on a second error signal derived from a difference between the feedback digital signal and a sum of the precompensated digital signal and the estimate of the distortions.

28. The system of claim 24 , wherein the model adaptor is configured to update the model based on a second error signal derived from a difference between the estimate of the distortions and a difference of the feedback digital signal and the precompensated digital signal.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
Continuity (5)
Division 12658498 · Feb 9, 2010
Division 12218032 · Jul 9, 2008
Division 11091022 · Mar 24, 2005
Provisional Application 60556658 · Mar 25, 2004
Related Publication 20120046925A1 · Feb 23, 2012