SYSTEM AND METHOD FOR PROTECTING A COMPUTING DEVICE USING VSD MATERIAL, AND METHOD FOR DESIGNING SAME
Embodiments described herein provide for programmatic design or simulation of substrates carrying electrical elements to integrate voltage switchable dielectric (“VSD”) material as a protective feature. In particular, VSD material may be incorporated into the design of a substrate device for purpose of providing protection against transient electrical conditions, such as electrostatic discharge (ESD).
1 . A computer implemented method for designing an electronic device, the method being implemented by one or more processors and comprising:
(a) designing the electronic device to include an embedded electrostatic discharge(ESD) component in electrical communication with an electronic component; and
(b) selecting one or more impedance elements and positioning the one or more impedance elements in electrical communication with the embedded ESD component and with the electronic component,
wherein the embedded ESD component and the one or more impedance elements are adapted to protect the electronic component against an ESD pulse.
2 . The method of claim 1 , wherein the embedded ESD component includes a layer of voltage switchable dielectric (VSD) material.
3 . The method of claim 1 , wherein the embedded ESD component includes one or more components selected from a group consisting of a voltage switchable dielectric (VSD) component, a varistor material, a silicon diode, a metal oxide varistor, a transient voltage suppression (TVS) component, or a zener diode.
4 . The method of claim 1 , wherein (b) includes positioning the one or more impedance elements to between the embedded ESD component and the electronic component.
5 . The method of claim 1 , wherein the electronic component corresponds to one of individual connector inputs (external and internal), buttons, antenna pads, touchscreens.
6 . A computer-implemented method for designing an electrical system of a device, the method comprising:
evaluating the electrical system, including multiple circuit elements and/or electrical components; and
determining, from analyzing the electrical system, (i) a first class of circuit elements and/or electrical components that satisfy one or more conditions for electrically connecting to voltage switchable dielectric (VSD) material for protection against electrical events that exceed a threshold; and (ii) a second class of circuit elements and/or electrical components that satisfy one or more conditions for not electrically connecting to VSD material.
7 . The method of claim 6 , further comprising enabling a designer to implement a design in which at least a first layer of VSD material is connected to individual circuit elements and/or electrical components of the first class.
8 . The method of claim 7 , further comprising simulating the electrical system of the device with the first layer of VSD material being connected to individual circuit elements and/or electrical components of the first class.
9 . The method of claim 6 , further comprising (iii) determining a third class of circuit elements and/or electrical components that satisfy one or more conditions of the first class for electrically connecting to VSD material, but which are negatively impacted in performance of functionality as a result of being positioned to electrically connect to VSD material.
10 . The method of claim 6 , wherein evaluating the electrical system includes simulating the electrical system of the device as a whole under presence of an ESD pulse.
11 . The method of claim 6 , wherein evaluating the electrical system includes simulating a portion of the electrical system of the device under presence of an ESD pulse.
12 . The method of claim 11 , wherein the portion of the electrical system includes one or more of a circuit element, a chip, an electrical circuit, and/or a mechanical component.
13 . The method of claim 12 , wherein evaluating the electrical system includes simulating one or more of a current response or frequency response to an electrostatic discharge (ESD) pulse by one or more circuit elements and/or electrical components of the electrical system.
14 . The method of claim 6 , wherein determining (ii) includes determining that a parasitic capacitance from presence of the VSD material is detrimental to performance of one or more of the circuit elements and/or electrical components of the second set.
15 . A system for protecting a computing device against harmful electrical events, the system comprising:
a plurality of electrical elements, including a first subset of electrical elements that are sensitive to electrical events that exceed at least a first threshold, and a second subset of electrical elements that are sensitive to electrical events that exceed at least a second threshold that is greater than the first threshold;
one or more layers of voltage switchable dielectric (VSD) material; and
one or more impedance elements that are selected and positioned to protect one or more of the electrical elements in the first subset.
16 . The system of claim 15 , wherein the one or more impedance elements are configured to guide a charge from an electrical event onto an electrical path that is connected to one or more of the layers of VSD material.
17 . A computing device comprising:
a plurality of electrical elements, including a first subset of electrical elements that are deemed to be sensitive to electrical events that exceed at least a first threshold, and a second subset of electrical elements that are deemed to be sensitive to electrical events that exceed at least a second threshold that is greater than the first threshold;
one or more layers of voltage switchable dielectric (VSD) material; and
one or more impedance elements that are selected and positioned to protect one or more of the electrical elements in the first subset.
18 . The computing device of claim 17 , wherein the one or more impedance elements are configured to guide a charge from an electrical event onto an electrical path that is connected to one or more of the layers of VSD material.
19 . The computing device of claim 17 , wherein one or more of the layers of VSD material are positioned to conduct current in response to an electrical event that originates from the operation of a display screen of the computing device.
20 . The computing device of claim 17 , wherein one or more of the layers of VSD material are positioned to conduct current in response to an electrical event that originates from the operation of an antenna element of the computing device.