Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
View Patent ↗Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
1. A memory cell comprising:
a memory element disposed to be selectively and reversibly configured in one of two or more different resistive states, the memory element comprising a first electrode and a second electrode;
a first diode comprising an anode and a cathode, the cathode of the first diode being connected to the first electrode of the memory element;
a second diode comprising an anode and a cathode, the anode of the second diode being connected to the first electrode of the memory element;
a first bitline connected to the anode of the first diode;
a second bitline connected to the cathode of the second diode; and
a wordline connected to the second electrode of the memory element.
2. The memory cell of claim 1 wherein the memory element comprises at least one of an ionic conducting chalcogenide, a binary metal oxide, a perovskite oxide, a colossal magnetoresistive, or a polymer.
3. A memory cell programming method comprising:
providing a memory cell comprising a first bitline, a second bitline, a wordline, and a memory element disposed to be selectively and reversibly configured in one of two different resistive states;
configuring the memory element in a first one of the resistive states by conducting current from the first bitline through the memory element to the wordline while preventing current from flowing to the second bitline; and
configuring the memory element in a second one of the resistive states by conducting current from the wordline through the memory element to the second bitline while preventing current from flowing to the first bitline.
4. The method of claim 3 wherein the memory cell further comprises a first diode connected between the first bitline and the memory element and a second diode connected between the second bitline and the memory element.
5. The method of claim 4 wherein preventing current from flowing to the second bitline comprises reverse biasing the second diode.
6. The method of claim 4 wherein preventing current from flowing to the first bitline comprises reverse biasing the first diode.
7. The method of claim 4 wherein a cathode of the first diode is connected to a first electrode of the memory element, an anode of the second diode is connected to the first electrode of the memory element, and a second electrode of the memory element is connected to the wordline.
8. The method of claim 3 wherein conducting current from the first bitline through the memory element to the wordline comprises forward biasing the first diode.
9. The method of claim 3 wherein conducting current from the wordline through the memory element to the second bitline comprises forward biasing the second diode.
10. The method of claim 3 wherein the memory element is highly conductive of current when the memory element is in the first one of the resistive states and the memory element is highly resistive of current when the memory element is in the second one of the resistive states.
11. A memory cell reading method comprising:
providing a memory cell comprising a first bitline, a second bitline, a wordline, and a memory element disposed to be selectively and reversibly configured in one of a plurality of different resistive states;
conducting current from the first bitline through the memory element to the wordline while preventing current from flowing to the second bitline; and
based on the current, determining that the memory element is configured in a particular one of the plurality of different resistive states.
12. The method of claim 11 wherein the memory cell further comprises a first selectively conducting device connected between the first bitline and a first electrode of the memory element and a second selectively conducting device connected between the second bitline and the first electrode of the memory element.
13. The method of claim 12 wherein preventing current from flowing to the second bitline comprises disabling the second selectively conducting device and conducting current from the first bitline through the memory element to the wordline comprises enabling the first selectively conducting device.
14. A memory cell reading method comprising:
providing a memory cell comprising a first bitline, a second bitline, a wordline, and a memory element disposed to be selectively and reversibly configured in one of a plurality of different resistive states;
conducting current from the wordline through the memory element to the second bitline while preventing current from flowing to the first bitline; and
based on the current, determining that the memory element is configured in a particular one of the plurality of different resistive states.
15. The method of claim 14 wherein the memory cell further comprises a first diode connected between the first bitline and the memory element and a second diode connected between the second bitline and the memory element.
16. The method of claim 15 wherein preventing current from flowing to the first bitline comprises reverse biasing the first diode.
17. The method of claim 15 wherein a cathode of the first diode is connected to a first electrode of the memory element, an anode of the second diode is connected to the first electrode of the memory element, and a second electrode of the memory element is connected to the wordline.
18. The method of claim 15 wherein conducting current from the wordline through the memory element to the second bitline comprises forward biasing the second diode.