Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
Methods and apparatuses that include resistive memory can include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.
1. An array of resistive memory cells, comprising:
a first memory cell coupled to a data line and including a first resistive storage element and a first access device;
a second memory cell coupled to the data line and including a second resistive storage element and a second access device;
an isolation device formed between the first access device and the second access device, wherein a gate of the isolation device is coupled to an isolation access line;
a first select line coupled to the first resistive storage element; and
a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.
2. The array of claim 1 , including a first access line coupled to a gate of the first access device and a second access line coupled to a gate of the second access device.
3. The array of claim 1 , wherein the first access device and the second access device are coupled to the data line.
4. The array of claim 1 , wherein the isolation device is a transistor.
5. The array of claim 4 , wherein the first access device, the second access device, and the isolation device are concurrently formed transistors.
6. The array of claim 5 , wherein the first access device, the second access device, and the isolation device are concurrently formed vertical field effect transistors.
7. The array of claim 1 , wherein the first and the second resistance storage elements are formed below the data line.
8. The array of claim 1 , wherein the first and the second resistance storage elements are formed above the data line.
9. The array of claim 1 , including an isolation line coupled to a gate of the isolation device and configured to receive a number of different applied signals responsive to a number of different memory operations performed on the first and the second memory cells.
10. A method of forming a resistive memory device, comprising:
forming a first memory cell coupled to a data line, wherein the first memory cells includes a first resistive storage element and a first access device;
forming a second memory cell coupled to the data line, wherein the second memory cells includes a second resistive storage element and a second access device;
forming an isolation device between the first access device and the second access device, wherein a gate of the isolation device is coupled to an isolation access line;
forming a first select line, wherein the first select line is coupled to the first resistive storage element; and
forming a second select line, wherein the second select line is coupled to the second resistive storage element and wherein the second select line is separate from the first select line.
11. The method of claim 10 , wherein the method includes forming a first access line coupled to a gate of the first access device and forming a second access line coupled to a gate of the second access device.
12. The method of claim 10 , wherein the first access device and the second access device are coupled to the data line.
13. The method of claim 10 , wherein the method includes forming the first access device, the second access device, and the isolation device concurrently.
14. The method of claim 10 , wherein the method includes forming the first and the second resistance storage elements below the data line.
15. The method of claim 10 , wherein the method includes forming the first and the second resistance storage elements above the data line.
16. The method of claim 10 , including forming the isolation device such that it is shared by the first and second memory cells in a 1.5T1R architecture.