Method and device employing polysilicon scaling
View Patent ↗A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
1. A memory, comprising:
a substrate;
one or more core memory cells that each include:
a charge trapping component located on a portion of the substrate,
wherein the charge trapping component includes a charge trapping layer; and
a portion of a word line residing on a portion of the charge trapping component, wherein the word line includes a portion of a core polysilicon layer; and
one or more peripheral devices residing on another portion of the substrate,
wherein the peripheral devices include a portion of a peripheral polysilicon layer, wherein the peripheral polysilicon layer is thicker than the core polysilicon layer,
wherein the portion of the core polysilicon layer has a different line profile than the portion of the peripheral polysilicon layer, and
wherein a height of the one or more core memory cells relative to a surface of the substate is different from a height of the one or more peripheral devices relative to surface of the substrate.
2. The memory of claim 1 , wherein the peripheral devices include:
a transistor configured to at least one of select a portion of the core memory cells for read/write access or provide an electrical signal to the core memory cells for at least one of programming or erasing.
3. The memory of claim 1 , wherein the one or more core memory cells each include a barrier layer, a charge trapping layer on the tunneling barrier, and a dielectric layer on the charge trapping layer, wherein the charge trapping layer is configured to store two logic states.
4. The memory of claim 1 , wherein the portion of the core polysilicon layer is different from the portion of the peripheral polysilicon layer in with respect to a presence of silicon nitride stringers.
5. The memory of claim 4 , wherein the portion of the core polysilicon layer has a different line aspect ratio than the portion of the peripheral polysilicon layer in line aspect ratios.
6. The memory of claim 1 , wherein the one or more peripheral devices comprise a transistor configured to provide read and write voltages in the range of 10V to 20V.
7. The memory of claim 1 , wherein the core polysilieon layer and the charge trapping component of the one or more core memory cells together form a layered stack and wherein the one or more core memory cells further comprise a dielectric spacer that seals spacings of the layered stack.
8. A memory, comprising:
a substrate;
one or more core memory cells that each include:
a charge trapping component located on a portion of the substrate, wherein the charge trapping component includes a charge trapping layer; and
a portion of a word line residing on a portion of the charge trapping component, wherein the word line includes a portion of a core polysilicon layer; and
one or more peripheral devices residing on another portion of the substrate, wherein the peripheral devices include a portion of a peripheral polysilicon layer, wherein the peripheral polysilicon layer is thicker than the core polysilicon layer, wherein the core polysilicon layer has a thickness in a range of about 300 to 900 Å, wherein the peripheral polysilicon layer has a thickness in range of about 1000 to 2000 Å, and wherein a height of the one or more core memory cells relative to a surface of the substrate is different from a height of the one or more peripheral devices relative to the surface of the substrate.
9. A memory, comprising:
a substrate;
one or more core memory cells that each include:
a charge trapping component located on a portion of the substrate, wherein the charge trapping, component includes a charge trapping layer; and
a portion of a word line residing on a portion of the charge trapping component, wherein the word line includes a portion of a core polysilicon layer; and
one or more peripheral devices residing on another portion of the substrate,
wherein the peripheral devices include a portion of a peripheral polysilicon layer, wherein the peripheral polysilicon layer is thicker than the core polysilicon layer,
wherein the memory cells are arrayed according to a first pitch,
wherein the peripheral devices are arrayed according to a second pitch that is greater than the first pitch, and
wherein a height of the one or more core memory cells relative to a surface of the substrate is different from a height of the one or more peripheral devices relative to the surface of the substrate.
10. A memory; comprising:
a substrate;
one or more core memory cells that each include:
a charge trapped component located on a portion of the substate, wherein the charge trapping component includes a charge trapping layer; and
a portion of a word line residing on a portion of the charge trapping component, wherein the word line includes a portion of a core polysilicon layer; and
one or more peripheral devices residing on another portion of the substrate, wherein the peripheral devices include a portion of a peripheral polysilicon layer,
wherein the core polysilicon layer has a thickness less than 1000 Å,
wherein the peripheral polysilicon layer has a thickness greater than 1000 Å, and
wherein a height of the one or more core memory cells relative to a surface of the substrate is different from a height of one or more peripheral devices relative to the surface of the substrate.