Methods of forming memory cells and methods of forming programmed memory cells

1. A method of programming a memory cell, comprising:

providing a memory cell which contains a transistor; the transistor including a transistor gate spaced from a channel region by a gate dielectric, including a first source/drain region on one side of the channel region, and including a second source/drain region on an opposing side of the channel region from the first source/drain region;

utilizing the first source/drain region as a source and the second source/drain region as a drain to induce one memory state of the memory cell; and

utilizing the second source/drain region as a source and the first source/drain region as a drain to induce another memory state of the memory cell;

wherein:

the channel region comprises a first volume of programmable material adjacent the first source/drain region;

the channel region comprises a second volume of programmable material adjacent the second source/drain region; and

the channel region comprises non-phase change material between the first and second volumes.

2. A method of forming a programmed memory cell, comprising:

forming a transistor which includes a transistor gate spaced from a channel region by a gate dielectric, and which includes a first source/drain region on one side of the channel region and a second source/drain region on an opposing side of the channel region from the first source/drain region; wherein the channel region comprises a first volume of programmable material adjacent the first source/drain region, comprises a second volume of programmable material adjacent the second source/drain region, and comprises non-phase change material between the first and second volumes;

forming a first inversion layer within the channel region adjacent the gate dielectric, the first inversion layer having a first pinch-off region within the first volume of programmable material;

utilizing hot carriers within the first pinch-off region to change a phase within the first volume of programmable material and thereby achieve a first memory state;

forming a second inversion layer within the channel region adjacent the gate dielectric, the second inversion layer having a second pinch-off region within the second volume of programmable material; and

utilizing hot carriers within the second pinch-off region to change a phase within the second volume of programmable material and thereby achieve a second memory state.

3. The method of claim 2 wherein the hot carriers are electrons.

4. The method of claim 2 wherein the first and second volumes of programmable materials consist of phase change material, and are of a common composition to one another.

5. A method of programming a memory cell, the memory cell comprising a transistor which includes a transistor gate spaced from a channel region by at least a gate dielectric, which includes a source region adjacent one side of the channel region, and which includes a drain region adjacent an opposing side of the channel region from the source region; wherein the channel region comprises phase change material adjacent at least the drain region, the method comprising:

utilizing the first source/drain region as a source and the second source/drain region as a drain to induce one memory state of the memory cell;

utilizing the second source/drain region as a source and the first source/drain region as a drain to induce another memory state of the memory cell; and

wherein the channel region primarily comprises non-phase change material.

6. A method of programming a memory cell, the memory cell comprising a transistor which includes a transistor gate spaced from a channel region by at least a gate dielectric, which includes a source region adjacent one side of the channel region, and which includes a drain region adjacent an opposing side of the channel region from the source region; wherein the channel region comprises phase change material adjacent at least the drain region, the method comprising:

forming an inversion layer within the channel region adjacent the gate dielectric, the inversion layer having a pinch-off region within the phase change material adjacent the drain region;

utilizing hot carriers within the pinch-off region to change a phase of the phase change material; and

wherein the channel region comprises non-phase change material.

7. The method of claim 6 wherein the change in phase decreases crystallinity of the phase change material.

8. The method of claim 6 wherein the change in phase increases crystallinity of the phase change material.

9. The method of claim 6 wherein the hot carriers are electrons.

10. The method of claim 6 wherein the hot carriers are holes.

11. The method of claim 6 wherein the channel region primarily comprises non-phase change semiconductor material, and comprises the phase change material only adjacent the drain region.

12. A method of programming a memory cell, the memory cell comprising a transistor which includes a transistor gate spaced from a channel region by a gate dielectric, and which includes a first source-and/or-drain region adjacent one side of the channel region and a second source-and/or-drain region adjacent an opposing side of the channel region from the first source-and/or-drain region; wherein the channel region comprises a first volume of programmable material adjacent the first source-and/or-drain region, and comprises a second volume of programmable material adjacent the second source-and/or-drain region, the method comprising:

forming a first inversion layer within the channel region adjacent the gate dielectric, the first inversion layer having a first pinch-off region within the first volume of programmable material, utilizing hot carriers within the first pinch-off region to change a phase within the first volume of programmable material and thereby correspond to a first memory state; and/or forming a second inversion layer within the channel region adjacent the gate dielectric, the second inversion layer having a second pinch-off region within the second volume of programmable material, utilizing hot carriers within the second pinch-off region to change a phase within the second volume of programmable material and thereby correspond to a second memory state; and

wherein the channel region primarily comprises non-phase change material and comprises the phase change material only adjacent the first and second source-and/or-drain regions.

13. A method of programming a memory cell; the memory cell comprising a transistor which includes a transistor gate spaced from a channel region by a gate dielectric, which includes a first source/drain region on one side of the channel region, and which includes a second source/drain region on an opposing side of the channel region from the first source/drain region; the method comprising:

utilizing the first source/drain region as a source and the second source/drain region as a drain to induce one memory state of the memory cell;

utilizing the second source/drain region as a source and the first source/drain region as a drain to induce another memory state of the memory cell;

wherein the channel region comprises a first volume of programmable material adjacent the first source/drain region, and comprises a second volume of programmable material adjacent the second source/drain region;

forming a first inversion layer within the channel region adjacent the gate dielectric, the first inversion layer having a first pinch-off region within the first volume of programmable material;

utilizing hot carriers within the first pinch-off region to change a phase within the first volume of programmable material and thereby achieve a first memory state;

forming a second inversion layer within the channel region adjacent the gate dielectric, the second inversion layer having a second pinch-off region within the second volume of programmable material; and

utilizing hot carriers within the second pinch-off region to change a phase within the second volume of programmable material and thereby achieve a second memory state.