Wide input voltage range power supply circuit
A wide input voltage power supply circuit for a load includes a first regulation stage and a second regulation stage. The first regulation stage includes a linear regulator circuit configured to maintain a bus voltage within a predefined voltage range when an input voltage exceeds a predefined input level. A second regulation stage includes a buck converter circuit configured to regulate an average bus voltage to a predetermined load level. The second regulation stage includes an under voltage lockout configuration, with the under voltage lockout configured to set a minimum turn-on voltage for the load.
1. A wide input voltage power supply circuit for a load, the circuit comprising:
a first regulation stage comprising a linear regulator circuit configured to maintain a bus voltage within a predefined voltage range when an input voltage exceeds a predefined input level, the linear regulator circuit comprising a first FET coupled to a first zener diode; and
a second regulation stage comprising a buck converter circuit configured to regulate an average bus voltage to a predetermined load level, and including an under voltage lockout configuration, the under voltage lockout configured to set a minimum turn-on voltage for the load, the under voltage lockout in series with a second zener diode so as to set the minimum turn-on voltage for the load.
2. The system according to claim 1 ,
wherein the predefined voltage range is between 80V and 120V when the predefined input level is about 120V.
3. The system according to claim 1 ,
wherein the input voltage range is between 24V AC/DC to 240V AC/DC.
4. The system according to claim 1 ,
wherein the load comprises a 12V relay.
5. A two stage relay control circuit comprising:
a relay including a relay coil;
a first regulation stage comprising a linear regulator circuit configured to maintain an input voltage at a regulated bus voltage between 80V and 120V when the input voltage exceeds a predefined input level, the linear regulator circuit comprising a first FET coupled to a first zener diode;
a second regulation stage comprising a buck converter circuit configured to further regulate an average bus voltage to a predetermined load level and to set a minimum turn-on voltage for the load, the minimum turn-on voltage for the relay coil being set with an under voltage lockout configuration, the under voltage lockout configuration in series with a second zener diode; and
an LED configured to indicate the conductive state of the two stage relay control circuit.
6. The system according to claim 5 ,
wherein the average bus voltage is regulated to a maximum coil voltage that the relay coil can tolerate.
7. The system according to claim 5 ,
wherein an input voltage range ratio is about 1:15.
8. A two stage relay control circuit comprising:
a relay including a relay coil;
a signal conditioning circuit configured to regulate an input voltage;
a rectifier circuit configured to rectify the input voltage;
a first regulation stage comprising a linear regulator circuit configured to maintain the input voltage at a regulated bus voltage between 80V and 120V when the input voltage exceeds a predefined input level, the linear regulator circuit comprising a FET coupled to a first zener diode;
a second regulation stage comprising a buck converter circuit configured to further regulate an average bus voltage to a predetermined relay coil level, and to set a minimum turn-on voltage for the relay coil, the minimum turn-on voltage being set with a second zener diode in series with an under voltage lockout configuration; and
an LED configured to indicate the conductive state of the two stage relay control circuit.
9. The system according to claim 8 ,
wherein the predefined input level is about 120V.
10. The system according to claim 8 ,
wherein the input voltage range ratio is about 1:15.
11. The system according to claim 8 ,
wherein the minimum turn-on voltage for the relay coil is set with an under voltage lockout configuration.
12. The system according to claim 8 ,
wherein the FET is a depletion mode FET.