Method of fabricating a semiconductor device having an epitaxy region

1. A method, comprising:

providing a substrate;

forming a first trench and a second trench in the semiconductor substrate, wherein the second trench has a greater width than the first trench;

growing a first epitaxy region in the first trench, wherein the epitaxy region extends beyond an opening of the first trench;

concurrently with growing the first epitaxy region, growing a second epitaxy region in the second trench, wherein a first portion of the second trench is not filled with the epitaxy region;

forming an amorphous layer overlying the second epitaxy region;

annealing the semiconductor substrate including the amorphous layer, wherein the annealing provides a crystalline region overlying the second epitaxy region; and

performing a chemical mechanical polish (CMP) after annealing the semiconductor substrate such than the first and second epitaxy regions are co-planar.

2. The method of claim 1 , wherein the performing the CMP provides a planar surface including a top surface of each of the first and second epitaxy regions and a top surface of an interposing isolation region.

3. The method of claim 1 , wherein the amorphous layer is between approximately 200 nanometers (nm) and approximately 500 nm in thickness.

4. The method of claim 1 , wherein the amorphous layer is less than 1 micron in thickness.

5. The method of claim 1 , wherein the amorphous layer includes germanium.

6. The method of claim 5 , wherein the first and second epitaxy regions include germanium.

7. The method of claim 1 , wherein the forming the first trench and the second trench and the growing the first and second epitaxy regions are performed in-situ.

8. The method of claim 7 , wherein the forming the first and second trenches includes:

forming a plurality of shallow trench isolation (STI) features in the substrate; and

removing a portion of the substrate interposing the STI features to form the first and second trenches.

9. A method, comprising:

providing a substrate having a first trench and a second trench;

growing an epitaxy material in the first trench, wherein the epitaxy material is a crystalline semiconductor material;

growing the epitaxy material in the second trench, wherein a top surface of the epitaxy material in the first trench is noncollinear with a top surface of the epitaxy material in the second trench;

forming an amorphous semiconductor layer on the epitaxy material; and

converting a portion of the amorphous semiconductor layer into the crystalline semiconductor material.

10. The method of claim 9 , wherein after the converting the portion of the amorphous semiconductor layer, a top surface of the crystalline semiconductor material disposed above the first trench is noncollinear with a top surface of the crystalline semiconductor material disposed above the second trench.

11. The method of claim 10 , further comprising:

performing a planarization process, wherein the planarization process provides a top surface of the crystalline semiconductor material disposed in the first trench collinear with a top surface of the crystalline semiconductor material disposed in the second trench.

12. The method of claim 9 , wherein the first and second trench include different dimensions.

13. The method of claim 9 , wherein the converting the portion of the amorphous semiconductor layer into the crystalline semiconductor material includes converting a portion of the amorphous semiconductor layer disposed in the first trench.

14. The method of claim 9 , wherein the first trench and the second trench include substantially tapered sidewalls.

15. The method of claim 9 , further comprising:

forming a gate structure on the converted portion of the amorphous semiconductor layer into the crystalline semiconductor material.

16. A method, comprising:

forming a first region of a crystalline material on a substrate;

forming an amorphous semiconductor layer on the first region;

converting at least a portion of the amorphous semiconductor layer to the crystalline material; and

thereafter, etching an adjacent insulating layer to provide a raised element of the crystalline material, wherein the raised element includes a fin of the finFET element.

17. The method of claim 16 , further comprising:

performing a planarization process, wherein the planarization includes removing the amorphous semiconductor layer after the converting such that the crystalline material is coplanar with an adjacent insulating layer; and

wherein the etching the adjacent insulating layer to provide the raised element is performed after the planarization process.

18. The method of claim 16 , wherein a channel of a device is formed in the raised element.

19. The method of claim 16 , wherein the forming the first region of the crystalline material includes epitaxially growing germanium.