IP Library Granted Patent US 8,912,024
Granted Patent B2
US 8,912,024 · App. 13/299,672 · Granted Dec 16, 2014

Front facing piggyback wafer assembly

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Quick Facts
Patent No.
US 8,912,024
App. No.
13/299,672
Granted
Dec 16, 2014
Kind
B2
Abstract

Front facing piggyback wafer assembly. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. The plurality of integrated circuit devices are singulated to form individual integrated circuit devices. The carrier wafer may be processed to form integrated circuit structures prior to the attaching.

Claims (33)

1. A method comprising:

attaching a plurality of piggyback substrates to a carrier wafer, wherein said plurality of piggyback substrates are dissimilar in composition to said carrier wafer;

forming and processing an active layer on said plurality of piggyback substrates, while attached to said carrier wafer, to produce a plurality of integrated circuit devices included in said active layer ; and

singulating said plurality of integrated circuit devices to form individual integrated circuit devices.

2. The method of claim 1 wherein said forming and processing takes place on manufacturing equipment designed to process wafers larger than said plurality of piggyback substrates.

3. The method of claim 1 wherein said plurality of piggyback substrates comprises a plurality of wafers.

4. The method of claim 1 further comprising processing said carrier wafer, prior to said attaching, to form integrated circuit structures.

5. The method of claim 1 further comprising singulating said plurality of piggyback substrates from a plurality of wafers prior to said attaching.

6. The method of claim 1 further comprising processing said carrier wafer, after said attaching, to form integrated circuit structures.

7. The method of claim 1 wherein said individual integrated circuit devices comprise a portion of said carrier wafer after said singulating said plurality of integrated circuit devices.

8. The method of claim 1 wherein said plurality of integrated circuit devices are of more than one design.

9. A method comprising:

attaching a plurality of piggyback substrates to a carrier wafer, wherein said plurality of piggyback substrates are dissimilar in composition to said carrier wafer;

forming and processing an active layer on said plurality of piggyback substrates, while attached to said carrier wafer, to produce a plurality of integrated circuit devices included in said active layer;

processing said carrier wafer to produce a plurality of integrated circuit structures; and

singulating said plurality of integrated circuit devices to form individual integrated circuit devices.

10. The method of claim 9 wherein said processing said carrier wafer occurs while said plurality of piggyback substrates are attached to said carrier wafer.

11. The method of claim 10 wherein said plurality of integrated circuit structures formed on said carrier wafer are electrically coupled to said plurality of integrated circuit devices formed on said plurality of piggyback substrates.

12. The method of claim 9 wherein said plurality of integrated circuit structures formed on said carrier wafer are formed outside of a vertical projection of said plurality of piggyback substrates.

13. The method of claim 12 wherein said individual integrated circuit devices comprise structures formed outside of the vertical projection of said plurality of piggyback substrates.

14. The method of claim 9 wherein said plurality of integrated circuit structures formed by said processing said carrier wafer comprise structures to couple power from said carrier wafer to said plurality of integrated circuit devices formed on said plurality of piggyback substrates.

15. The method of claim 9 wherein said plurality of integrated circuit structures formed by said processing said carrier wafer comprise power control electronics to couple power from said carrier wafer to said plurality of integrated circuit devices formed on said plurality of piggyback substrates.

16. A method comprising:

attaching a plurality of piggyback substrates to a carrier wafer, wherein said plurality of piggyback substrates are dissimilar in composition to said carrier wafer;

forming and processing an active layer on said plurality of piggyback substrates, while attached to said carrier wafer, to produce a plurality of light emitting diodes included in said active layer;

forming conductive structures through said carrier wafer to electrically couple to contacts of said plurality of light emitting diodes; and

singulating said plurality of light emitting diodes to form individual light emitting diode devices.

17. The method of claim 16 further comprising forming a plurality of package contacts on said carrier wafer to electrically couple to said conductive structures.

18. The method of claim 17 wherein said plurality of package contacts are on a back side of said carrier wafer.

19. The method of claim 16 further comprising forming a plurality of optical layers on top of said plurality of light emitting diodes.

20. The method of claim 19 wherein at least one of said plurality of optical layers comprises a lens.

21. The method of claim 16 wherein said conductive structures extend beyond said carrier wafer to electrically couple active layers of said plurality of light emitting diodes.

22. The method of claim 21 further comprising encapsulating said plurality of light emitting diodes and said conductive structures.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073689/0754 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073689/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2011
From: MOHAMMED, ILYAS; BEROZ, MASUD; WANG, LIANG
To: INVENSAS CORPORATION
Reel/Frame 027252/0469 →