Patent Assignment
Reel/Frame 073689/0786
Change of Name
Recorded: 2025-11-24
Pages: 7
Assignor
INVENSAS LLC
Executed: 2022-08-15
Assignee
ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(90)
Low Cte Interposer
Microelectronic Package with Stacked Microelectronic Units and Method for Manufacture Thereof
Non-Volatile Memory Devices Having Vertical Drain to Gate Capacitive Coupling
Common Doped Region with Separate Gate Control for a Logic Compatible Non-Volatile Memory Cell
High Strength Through-Substrate Vias
Cavities Containing Multi-Wiring Structures and Devices
Front Facing Piggyback Wafer Assembly
Stub Minimization for Multi-Die Wirebond Assemblies with Parallel Windows
Stub Minimization for Multi-Die Wirebond Assemblies with Parallel Windows
Patent:
8,345,441 →
Application:
13/337,575 →
Stackable Microelectronic Package Structures
Memory Module in a Package
Optical Interposer
Heat Spreading Substrate
Heat Spreading Substrate with Embedded Interconnects
Heat Spreading Substrate
Method for Package-on-Package Assembly with Wire Bonds to Encapsulation Surface
Patent:
8,372,741 →
Application:
13/405,125 →
Stub Minimization for Wirebond Assemblies Without Windows
Stub Minimization for Multi-Die Wirebond Assemblies with Parallel Windows
Structures Formed Using Monocrystalline Silicon and/or Other Materials for Optical and Other Applications
High Yield Substrate Assembly
Substrate-Less Stackable Package with Wire-Bond Interconnect
Tsv Fabrication Using a Removable Handling Structure
Reduced Stress Tsv and Interposer Structures
Microelectronic Assembly Tolerant to Misplacement of Microelectronic Elements Therein
Quantum Efficiency of Multiple Quantum Wells
Parallel Plate Slot Emission Array
Method of Processing a Device Substrate
Via in Substrate with Deposited Layer
Reconstituted Wafer-Level Package Dram
Thin Wafer Handling and Known Good Die Test Method
Tunable Composite Interposer
Stub Minimization with Terminal Grids Offset from Center of Package
Z-Connection Using Electroless Plating
High Performance Package on Package
Method for Package-on-Package Assembly with Wire Bonds to Encapsulation Surface
Method of Making Wire Bond Vias and Microelectronic Package Having Wire Bond Vias
Microelectronic Package Having Wire Bond Vias and Stiffening Layer
Carrier-Less Silicon Interposer
Manufacture of Face-Down Microelectronic Packages
High Yield Substrate Assembly
Parallel Plate Slot Emission Array
Stub Minimization for Assemblies Without Wirebonds to Package Substrate
Chips with High Fracture Toughness Through a Metal Ring
Methods of Fabricating a Flip Chip Package for Dram with Two Underfill Materials
Stub Minimization Using Duplicate Sets of Terminals Having Modulo-X Symmetry for Wirebond Assemblies Without Windows
Reduced Stress Tsv and Interposer Structures
Stackable Microelectronic Package Structures
Microelectronic Package with Stacked Microelectronic Units and Method for Manufacture Thereof
Microelectronic Assembly Including Memory Packages Connected to Circuit Panel, the Memory Packages Having Stub Minimization for Wirebond Assemblies Without Windows
Stub Minimization for Multi-Die Wirebond Assemblies with Parallel Windows
Method of Processing a Device Substrate
Low Cte Interposer
High Strength Through-Substrate Vias
Method for Package-on-Package Assembly with Wire Bonds to Encapsulation Surface
Memory Module in a Package
Substrate-Less Stackable Package with Wire-Bond Interconnect
Thin Wafer Handling and Known Good Die Test Method
Stub minimization for multi-die wirebond assemblies with parallel windows
Stackable microelectronic package structures
Cavities Containing Multi-Wiring Structures and Devices
Heat spreading substrate with embedded interconnects
Via in Substrate with Deposited Layer
Tunable Composite Interposer
Quantum Efficiency of Multiple Quantum Wells
Stackable Microelectronic Package Structures
Z-Connection for a Microelectronic Package Using Electroless Plating
On-Chip Impedance Network with Digital Coarse and Analog Fine Tuning
Method of Forming a Component Having Wire Bonds and a Stiffening Layer
Microelectronic Package with Stacked Microelectronic Units and Method for Manufacture Thereof
Substrate-less Stackable Package with Wire-Bond Interconnect
Memory Module in a Package
Microelectronic Assembly with Opposing Microelectronic Packages Each Having Terminals with Signal Assignments That Mirror Each Other with Respect to a Central Axis
Method for Package-on-Package Assembly with Wire Bonds to Encapsulation Surface
Stub Minimization for Assemblies Without Wirebonds to Package Substrate
Tunable Composite Interposer
Reconstituted Wafer-Level Package Dram with Conductive Interconnects Formed in Encapsulant at Periphery of the Package
Low Cte Interposer
Microelectronic Package Having Stub Minimization Using Symmetrically-Positioned Duplicate Sets of Terminals for Wirebond Assemblies Without Windows
Microelectronic Package with Stacked Microelectronic Units and Method for Manufacture Thereof
High Yield Substrate Assembly
Microelectronic Package Including Microelectronic Elements Having Stub Minimization for Wirebond Assemblies Without Windows
On-Chip Impedance Network with Digital Coarse and Analog Fine Tuning
Low Cte Interposer
Stackable Microelectronic Package Structures
Substrate-Less Stackable Package with Wire-Bond Interconnect
Cavities Containing Multi-wiring Structures And Devices
Microelectronic Package Having Stub Minimization Using Symmetrically-Positioned Duplicate Sets of Terminals for Wirebond Assemblies Without Windows
Microelectronic Package Including Microelectronic Elements Having Stub Minimization For Wirebond Assemblies Without Windows
Substrate-Less Stackable Package with Wire-Bond Interconnect
High Yield Substrate Assembly
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 19, 2011
From: HABA, BELGACEM; DESAI, KISHOR
To: INVENSAS CORP.
Reel/Frame 026954/0137 →
Assignment of Assignor's Interest
Nov 18, 2011
From: MOHAMMED, ILYAS; BEROZ, MASUD; WANG, LIANG
To: INVENSAS CORPORATION
Reel/Frame 027252/0469 →
Assignment of Assignor's Interest
Jan 17, 2012
From: FISCH, DAVID EDWARD; PARRIS, MICHAEL CURTIS
To: INVENSAS CORPORATION
Reel/Frame 027545/0714 →
Assignment of Assignor's Interest
Feb 23, 2012
From: CRISP, RICHARD DEWITT; ZOHNI, WAEL; HABA, BELGACEM; LAMBRECHT, FRANK
To: INVENSAS CORPORATION
Reel/Frame 027762/0615 →
Assignment of Assignor's Interest
Feb 23, 2012
From: CRISP, RICHARD DEWITT; ZOHNI, WAEL; HABA, BELGACEM; LAMBRECHT, FRANK
To: INVENSAS CORPORATION
Reel/Frame 027762/0570 →
Assignment of Assignor's Interest
Feb 29, 2012
From: CO, REYNALDO; MIRKARIMI, LAURA
To: INVENSAS CORPORATION
Reel/Frame 027801/0403 →
Assignment of Assignor's Interest
Mar 7, 2012
From: CASKEY, TERRENCE; MOHAMMED, ILYAS
To: INVENSAS CORPORATION
Reel/Frame 027845/0158 →
Assignment of Assignor's Interest
Apr 4, 2012
From: KOSENKO, VALENTIN; MCBAIN, EDWARD LEE; UZOH, CYPRIAN EMEKA; MONADGEMI, PEZHMAN
To: INVENSAS CORPORATION
Reel/Frame 027990/0715 →
Assignment of Assignor's Interest
Apr 10, 2012
From: HABA, BELGACEM; ZOHNI, WAEL; CRISP, RICHARD DEWITT; MOHAMMED, ILYAS
To: INVENSAS CORPORATION
Reel/Frame 028031/0209 →
Assignment of Assignor's Interest
Apr 10, 2012
From: CRISP, RICHARD DEWITT; ZOHNI, WAEL; HABA, BELGACEM; LAMBRECHT, FRANK
To: INVENSAS CORPORATION
Reel/Frame 028031/0143 →
Assignment of Assignor's Interest
Apr 16, 2012
From: HABA, BELGACEM; BANG, KYONG-MO
To: INVENSAS CORPORATION
Reel/Frame 028071/0961 →
Assignment of Assignor's Interest
Apr 30, 2012
From: UZOH, CYPRIAN; MITCHELL, CRAIG; HABA, BELGACEM; MOHAMMED, ILYAS
To: INVENSAS CORPORATION
Reel/Frame 028146/0684 →
Assignment of Assignor's Interest
May 2, 2012
From: GUEVARA, GABRIEL Z.
To: INVENSAS CORPORATION
Reel/Frame 028143/0059 →
Assignment of Assignor's Interest
Jun 5, 2012
From: GUEVARA, GABRIEL Z.; MOHAMMED, ILYAS; WANG, LIANG
To: INVENSAS CORPORATION
Reel/Frame 028322/0760 →
Assignment of Assignor's Interest
Jul 3, 2012
From: MOHAMMED, ILYAS; BEROZ, MASUD
To: INVENSAS CORPORATION
Reel/Frame 028486/0735 →
Assignment of Assignor's Interest
Jul 23, 2012
From: FISCH, DAVID EDWARD; PLANTS, WILLIAM C.; PARRIS, MICHAEL CURTIS
To: INVENSAS CORPORATION
Reel/Frame 028617/0001 →
Assignment of Assignor's Interest
Aug 30, 2012
From: UZOH, CYPRIAN EMEKA; MONADGEMI, PEZHMAN
To: INVENSAS CORPORATION
Reel/Frame 028876/0134 →
Assignment of Assignor's Interest
Aug 30, 2012
From: KOSENKO, VALENTIN; MCBAIN, EDWARD LEE; SAVASTIOUK, SERGEY
To: ALLVIA, INC.
Reel/Frame 028876/0068 →
Assignment of Assignor's Interest
Aug 30, 2012
From: ALLVIA, INC.
To: INVENSAS CORPORATION
Reel/Frame 028876/0168 →
Assignment of Assignor's Interest
Sep 28, 2012
From: UZOH, CYPRIAN EMEKA; WOYCHIK, CHARLES G.; CASKEY, TERRENCE; HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 029072/0746 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Assignment of Assignor's Interest
Jul 17, 2019
From: WANG, LIANG; MOHAMMED, ILYAS; BEROZ, MASUD
To: INVENSAS CORPORATION
Reel/Frame 049777/0278 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →
Change of Name
Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073689/0754 →