IP Library Granted Patent US 8,835,228
Granted Patent B2
US 8,835,228 · App. 13/477,532 · Granted Sep 16, 2014

Substrate-less stackable package with wire-bond interconnect

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Quick Facts
Patent No.
US 8,835,228
App. No.
13/477,532
Granted
Sep 16, 2014
Kind
B2
Abstract

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

Claims (37)

1. A method for making a microelectronic unit, comprising the steps of:

forming a plurality of wire bonds on a first surface that is a conductive bonding surface of a structure comprising a patternable metallic element, the wire bonds having bases joined to the first surface and end surfaces remote from the bases and remote from the first surface, the wire bonds further having edge surfaces extending between the bases and the end surfaces;

forming a dielectric encapsulation layer over at least a portion of the first surface of the conductive layer and over portions of the wire bonds, such that unencapsulated portions of the wire bonds are defined by at least one of the end surface or a portion of the edge surface thereof that is uncovered by the encapsulation layer; and

then patterning the metallic element selectively to form first conductive elements insulated from one another by at least portions of the encapsulation layer, wherein at least some of the wire bonds are disposed atop the first conductive elements.

2. The method of claim 1 , wherein a microelectronic element is included in the structure and is electrically connected with the conductive layer when the step of removing portions of the conductive layer is performed.

3. The method of claim 2 , wherein the step of forming the dielectric encapsulation layer is carried out with the microelectronic element electrically connected with the conductive layer and such that the encapsulation layer at least partially covers at least one surface thereof.

4. The method of claim 2 , wherein at least some of the first conductive elements are electrically connected between respective ones of the wire bonds and the microelectronic element.

5. The method of claim 1 , further including the step of forming a redistribution layer over the second surface of the encapsulation layer, the redistribution layer including conductive contacts displaced in at least one lateral direction from the unexposed portions of the wire bonds.

6. The method of claim 1 , wherein at least some of the wire bonds are formed such that the end surfaces thereof are displaced in one or more lateral directions from the bases thereof.

7. The method of claim 1 , wherein the bases are arranged in a first pattern having a first minimum pitch and wherein the unencapsulated portions of the wire bonds are arranged in a pattern having a second minimum pitch that is greater than the first minimum pitch.

8. The method of claim 1 , wherein the bases are arranged in a first pattern having a first minimum pitch and wherein the unencapsulated portions of the wire bonds are arranged in a pattern having a second minimum pitch that is less than the first minimum pitch.

9. The method of claim 1 , wherein the bases of the wire bonds are in the form of ball bonds.

10. The method of claim 1 , wherein the edge surfaces of the wire bonds extending between the bases and the end surfaces are first edge surface portions, and wherein the bases of the wire bonds are second portions of the edge surfaces that extend along the first conductive elements.

11. The method of claim 1 , further including forming second conductive elements overlying the second surface of the dielectric layer, at least some of the second conductive elements being connected with respective ones of at least some of the unencapuslated portions of the wire bonds.

12. The method of claim 1 , wherein the step of selectively removing portions of the conductive layer includes forming at least some first conductive elements as contact pads to which bases of wire bonds that are not electrically connected with other elements of the unit are electrically connected.

13. The method of claim 1 , further including the step of thinning the unit by one of grinding or polishing.

14. The method of claim 13 , wherein the encapsulation layer is formed having an initial thickness such that the end surfaces of the wire bonds are substantially covered, and wherein the step of thinning the unit includes removing a portion of the encapsulation layer such that the end surfaces are unencapsualted by the encapsulation layer.

15. The method of claim 1 , wherein the step of forming the encapsulation layer includes dispensing an encapsulant onto the first surface of the conductive layer and at least edge surfaces of the wire bonds.

16. The method of claim 2 , wherein the step of forming the encapsulation layer includes molding an encapsulant in contact with the conductive layer, at least edge surfaces of the wire bonds, and at least surface of the microelectronic element.

17. The method of claim 1 , further including removing a carrier from a surface of the conductive layer opposite the wire bonds prior to performing the step of selectively removing portions of the conductive layer.

18. The method of claim 17 , wherein the conductive layer has a thickness of less than 20 microns.

19. A method for making a microelectronic package, comprising the steps of:

forming a plurality of wire bonds on a first surface of a conductive layer of an in process unit, the in-process unit having at least one microelectronic element joined thereto and electrically connected with portions thereof, the wire bonds being formed having bases joined to the first surface and end surfaces remote from the bases and remote from the first surface, the wire bonds further having edge surfaces extending between the bases and the end surfaces;

forming a dielectric encapsulation layer over at least a portion of the first surface of the conductive layer, over at least a portion of the at least one microelectronic element, and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by at least one of the end surface or a portion of the edge surface thereof that is uncovered by the encapsulation layer; and

selectively removing portions of the conductive layer to form first conductive elements thereof, wherein at least some of the first conductive elements are electrically connected with at least some of the wire bonds and at least some of the first conductive elements include at least some of the portions of the conductive layer with which the microelectronic element is electrically connected.

20. A method for making a microelectronic unit, comprising the steps of:

forming a plurality of wire bonds on a first surface that is a conductive bonding surface of structure comprising a patternable metallic element, the wire bonds having bases joined to the first surface and end surfaces remote from the bases and remote from the first surface, the wire bonds further having edge surfaces extending between the bases and the end surfaces, wherein when forming the wire bonds, the conductive layer includes a plurality of regions attached to one another at at least some edges thereof;

forming a dielectric encapsulation layer over at least a portion of the first surface of the conductive layer and over portions of the wire bonds, such that unencapsulated portions of the wire bonds are defined by at least one of the end surface or a portion of the edge surface thereof that is uncovered by the encapsulation layer, wherein when performing the step of selectively removing portions of the encapsulation layer, a plurality of microelectronic elements are joined to the conductive layer, in the form of an in-process unit having at least one microelectronic element electrically connected with each of at least some of the regions of the conductive layer;

then patterning the metallic element selectively to form first conductive elements insulated from one another by at least portions of the encapsulation layer, wherein at least some of the wire bonds are disposed atop the first conductive elements; and

then severing the in-process unit into a plurality of microelectronic units, each including the first conductive elements of a region of the conductive layer and the at least one microelectronic element electrically connected therewith.

21. A method for making a microelectronic assembly, comprising:

making a first microelectronic package by steps including:

forming a plurality of wire bonds on a first surface of a conductive layer of an in process unit, the in-process unit having at least one microelectronic element joined thereto and electrically connected with portions thereof, the wire bonds being formed having bases joined to the first surface and end surfaces remote from the bases and remote from the first surface, the wire bonds further having edge surfaces extending between the bases and the end surfaces;

forming a dielectric encapsulation layer over at least a portion of the first surface of the conductive layer, over at least a portion of the at least one microelectronic element, and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by at least one of the end surface or a portion of the edge surface thereof that is uncovered by the encapsulation layer; and

selectively removing portions of the conductive layer to form first conductive elements thereof, wherein at least some of the first conductive elements are electrically connected with at least some of the wire bonds and at least some of the first conductive elements include at least some of the portions of the conductive layer with which the microelectronic element is electrically connected; and

joining the first microelectronic package with a second microelectronic package overlying the second surface of the encapsulation layer of the first package, the second microelectronic package including a plurality of contacts exposed at a first surface thereof;

wherein joining the first microelectronic package with the second microelectronic package includes electrically connecting the unencapsulated portions of the wire bonds of the first microelectronic package with the contacts of the second microelectronic package.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073689/0754 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073689/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2012
From: MOHAMMED, ILYAS
To: INVENSAS CORPORATION
Reel/Frame 028850/0093 →