IP Library Granted Patent US 8,951,845
Granted Patent B2
US 8,951,845 · App. 14/163,145 · Granted Feb 10, 2015

Methods of fabricating a flip chip package for dram with two underfill materials

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Quick Facts
Patent No.
US 8,951,845
App. No.
14/163,145
Granted
Feb 10, 2015
Kind
B2
Abstract

A method of fabricating a microelectronic package can include mounting a microelectronic element to a substrate with a joining material. The mounting can include bonding a front surface of the microelectronic element to a first surface of the substrate with a joining material, and joining contacts arranged within a contact-bearing region of the front surface of the microelectronic element with corresponding substrate contacts at the substrate first surface, the joining creating electrical contact between the microelectronic element and the substrate. The method can also include forming an underfill between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element, the underfill reinforcing the joints between the contacts and the substrate contacts, the joining material having a Young's modulus less than 75% of a Young's modulus of the underfill.

Claims (31)

1. A method of fabricating a microelectronic package, comprising:

mounting a microelectronic element to a substrate with a joining material, the mounting including:

bonding a front surface of the microelectronic element to a first surface of the substrate with a joining material; and

joining contacts arranged within a contact-bearing region of the front surface of the microelectronic element with corresponding substrate contacts at the substrate first surface, the joining creating electrical contact between the microelectronic element and the substrate; and then

forming an underfill between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element, the underfill reinforcing the joints between the contacts and the substrate contacts, the joining material having a Young's modulus less than 75% of a Young's modulus of the underfill,

wherein the substrate has a second surface opposite the first surface and further includes at least one aperture extending between the first and second surfaces, and at least a portion of the underfill is formed extending through the at least one aperture.

2. A method as claimed in claim 1 , wherein at least a portion of the bonding and joining steps are performed simultaneously.

3. A method as claimed in claim 1 , wherein the Young's modulus of the underfill is greater than 5 GPa, and the Young's modulus of the joining material is less than 5 GPa.

4. A method as claimed in claim 1 , wherein the underfill is a different material than the joining material.

5. A method as claimed in claim 1 , wherein the underfill is a no-flow underfill.

6. A method as claimed in claim 1 , wherein the joining material is disposed adjacent first and second opposed edges of the contact-bearing region.

7. A method as claimed in claim 1 , further comprising forming an overmold region overlying a rear surface of the microelectronic element and the first surface of the substrate.

8. A method as claimed in claim 1 , wherein the contact-bearing region extends up to one-third of a distance between first and second opposed edges of the front surface of the microelectronic element.

9. A method as claimed in claim 1 , wherein the microelectronic element embodies a greater number of active devices to provide memory storage array function than any other function.

10. A method as claimed in claim 1 , wherein the contact-bearing region is entirely located within a middle third of a distance between first and second opposed edges of the front surface of the microelectronic element, wherein the at least one aperture overlies at least a portion of the contact-bearing region, and wherein the portion of the underfill that is formed extending through the at least one aperture is formed in contact with the contact-bearing region.

11. A method as claimed in claim 1 , wherein the mounting step includes joining the contacts of the microelectronic element to the substrate contacts with electrically conductive masses.

12. A method as claimed in claim 11 , wherein material of the underfill flows between adjacent ones of the conductive masses during the step of forming the underfill.

13. A method as claimed in claim 1 , wherein the contact-bearing region is entirely located within a middle third of a distance between the first and second opposed edges of the front surface of the microelectronic element.

14. A method as claimed in claim 1 , wherein the front surface of the microelectronic element further includes first and second peripheral regions between the contact-bearing region and first and second opposed edges of the front surface of the microelectronic element, and the underfill does not contact the first and second peripheral regions.

15. A method as claimed in claim 1 , wherein the underfill surrounds the joints in the contact-bearing region.

16. A method of fabricating a microelectronic package, comprising:

mounting a microelectronic element to a substrate with a joining material, the mounting including:

bonding a front surface of the microelectronic element to a first surface of the substrate with a joining material; and

joining contacts arranged within a contact-bearing region of the front surface of the microelectronic element with corresponding substrate contacts at the substrate first surface, the joining creating electrical contact between the microelectronic element and the substrate; and then

forming an underfill between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element, the underfill reinforcing the joints between the contacts and the substrate contacts, the joining material having a Young's modulus less than 75% of a Young's modulus of the underfill,

wherein the contact-bearing region is entirely located within a middle third of a distance between the first and second opposed edges of the front surface of the microelectronic element, and

wherein the front surface of the microelectronic element further includes first and second peripheral regions between the contact-bearing region and first and second opposed edges of the front surface of the microelectronic element, and the underfill does not contact the first and second peripheral regions.

17. A method as claimed in claim 16 , wherein the underfill surrounds the joints in the contact-bearing region.

18. A method as claimed in claim 16 , wherein the Young's modulus of the underfill is greater than 5 GPa, and the Young's modulus of the joining material is less than 5 GPa.

19. A method as claimed in claim 16 , wherein the underfill is a different material than the joining material.

20. A method as claimed in claim 16 , wherein the underfill is a no-flow underfill.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073689/0754 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073689/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2014
From: SAKUMA, KAZUO; MOHAMMED, ILYAS; DAMBERG, PHILIP
To: INVENSAS CORPORATION
Reel/Frame 033932/0221 →