Tunable composite interposer

1. A method of fabricating a microelectronic assembly, comprising:

uniting exposed surfaces of at least one of dielectric or semiconductor material of a substrate element and a support element with one another, the uniting including forming a bond between the exposed surfaces of the substrate element and the support element using one or more layers of dielectric material;

the substrate element having first and second opposite surfaces defining a thickness, and having a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness, the exposed surface of the at least one of dielectric or semiconductor material of the substrate element being the second surface thereof, and

the support element having a body having first and second opposite surfaces, and having electrically conductive vias extending between the first and second surfaces of the support element through a thickness of the body, the exposed surface of the at least one of dielectric or semiconductor material of the support element being the second surface thereof; and

after uniting the exposed surfaces of the substrate element and the support element, applying heat to the one or more layers of dielectric material, wherein the one or more layers of dielectric material includes conductors providing direct electrical connection between the conductive vias and the electrically conductive structure,

wherein the conductors include conductive traces that are separated and insulated from one another by the one or more layers of dielectric material.

2. The method as claimed in claim 1 , wherein the one or more layers of dielectric material include an adhesive layer or a B-stage material layer.

3. The method as claimed in claim 1 , wherein the substrate element includes a semiconductor body, and one or more semiconductor devices are disposed in one or more active device regions of the semiconductor body located at or below the first surface of the substrate element.

4. The method as claimed in claim 1 , wherein the support element has openings extending between the first and second surfaces of the support element through the thickness of the body, the method further comprising forming the electrically conductive vias extending within the openings.

5. The method as claimed in claim 4 , wherein each of at least some of the electrically conductive vias is separated by a compliant dielectric material from an inner surface of the opening in which it extends.

6. The method as claimed in claim 4 , wherein the electrically conductive structure extending through the substrate element thickness includes a plurality of electrically conductive vias, and wherein a minimum pitch between any two adjacent ones of the conductive vias of the substrate element is less than or equal to a minimum pitch between any two adjacent ones of the electrically conductive vias extending through the openings of the support element.

7. The method as claimed in claim 4 , further comprising forming a compliant dielectric material extending within the openings, wherein the electrically conductive vias are formed extending within an aperture extending through the compliant dielectric material.

8. The method as claimed in claim 4 , further comprising forming terminals exposed at the first surface of the support element, the terminals being electrically connected with the contacts through the electrically conductive vias and the electrically conductive structure.

9. The method as claimed in claim 8 , wherein the steps of forming the conductive vias and the terminals forms at least some of the terminals integrally with the electrically conductive vias as ends of the electrically conductive vias.

10. The method as claimed in claim 8 , further comprising forming a compliant dielectric layer extending along the first surface of the support element.

11. The method as claimed in claim 10 , wherein at least some of the terminals at least partially overlie the compliant dielectric layer.

12. The method as claimed in claim 1 , wherein at least some of the electrically conductive vias are wire bonds.

13. The method as claimed in claim 1 , wherein the thickness of the substrate element between the first and second surfaces thereof is 200 microns or less.

14. The method as claimed in claim 1 , wherein the thickness of the substrate element is less than the thickness of the support element.

15. The method as claimed in claim 1 , wherein the thickness of the substrate element is less than one-fifth the thickness of the support element.

16. The method as claimed in claim 1 , wherein the thickness of the support element is at least 1.5 times the thickness of the substrate element, and wherein the Young's modulus of the support element is greater than 60 GPa.

17. The method as claimed in claim 1 , wherein the thickness of the support element is at least 1.5 times the thickness of the substrate element, and wherein the Young's modulus of the support element is at least 1.3 times the Young's modulus of the substrate.

18. The method as claimed in claim 1 , wherein the body of the support element has a CTE of less than 12 ppm/° C.

19. The method as claimed in claim 1 , further comprising assembling a microelectronic element with the substrate element, the microelectronic element having a surface bearing element contacts thereon, the assembling including electrically connecting at least some of the contacts of the substrate element with at least some of the element contacts.

20. The method as claimed in claim 8 , further comprising assembling a circuit panel with the support element, at least some of the terminals exposed at the first surface of the support element being joined to and electrically connected with panel contacts exposed at a surface of the circuit panel.