High yield substrate assembly
View Patent ↗High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.
1. A method comprising:
creating a plurality of structures to a surface of a substrate to form a substrate assembly, the substrate comprised of a first material;
forming a layer of crystalline material on the entire said surface, wherein said crystalline material accesses a crystal pattern of said substrate, the crystalline material layer comprised of a second material different from the first material; and
processing, after said creating, said substrate assembly to produce a plurality of integrated circuit devices on said crystalline material, wherein said plurality of structures localize a lattice mismatch or coefficient of thermal expansion mismatch characteristic at the interface between the first and second material, and comprise substrate material that is characterized as amorphous.
2. The method of claim 1 wherein said plurality of structures are operable to relieve thermal stress across said substrate during said processing.
3. The method of claim 1 wherein said creating comprises heating a portion of said surface.
4. The method of claim 1 wherein said plurality of structures interrupt a crystal structure of said surface.
5. The method of claim 1 wherein said creating comprises mechanically sawing said surface.
6. The method of claim 1 wherein said creating comprises a chemical etching of said surface.
7. The method of claim 1 wherein said creating comprises removing material from said surface via a laser.
8. The method of claim 1 wherein said creating comprises removing material from said surface via an ion beam.
9. The method of claim 1 wherein at least two of said plurality of integrated circuit devices are formed between adjacent instances of said plurality of structures.
10. The method of claim 1 wherein said plurality of structures are created above said surface of said substrate.
11. The method of claim 10 wherein said crystalline material is formed over said plurality of structures.
12. A method comprising:
creating a plurality of structures to a surface of a substrate to form a substrate assembly, the substrate comprised of a first material;
forming a layer of crystalline material on the entire said surface, wherein said crystalline material accesses a crystal pattern of said substrate, the crystalline material layer comprised of a second material different from the first material; and
processing, after said creating, said substrate assembly to produce a plurality of integrated circuit devices on said crystalline material, wherein said plurality of structures localize a lattice mismatch or coefficient of thermal expansion mismatch characteristic at the interface between the first and second material, wherein said plurality of structures are created above said surface of said substrate.
13. The method of claim 12 wherein said plurality of structures are operable to relieve thermal stress across said substrate during said processing.
14. The method of claim 12 wherein said creating comprises heating a portion of said surface.
15. The method of claim 12 wherein said creating comprises mechanically sawing said surface.
16. The method of claim 12 wherein said creating comprises a chemical etching of said surface.
17. The method of claim 12 wherein said creating comprises removing material from said surface via a laser.
18. The method of claim 12 wherein said creating comprises removing material from said surface via an ion beam.
19. The method of claim 12 wherein at least two of said plurality of integrated circuit devices are formed between adjacent instances of said plurality of structures.
20. The method of claim 12 wherein said plurality of structures comprise amorphous material.
21. The method of claim 12 wherein said crystalline material is formed over said plurality of structures.