Microelectronic package with stacked microelectronic units and method for manufacture thereof

1. A microelectronic package comprising:

a first microelectronic unit including: a first semiconductor chip having first chip contacts, and first unit contacts positioned at a surface of the first microelectronic unit and electrically coupled with the first chip contacts;

a second microelectronic unit including: a second semiconductor chip having a front surface and an edge extending away from the front surface, and second chip contacts at the front surface,

wherein the first and second microelectronic units are stacked without a substrate, such that one or more of the first unit contacts is positioned on a portion of the first microelectronic unit that extends beyond an edge of the second microelectronic unit; and

package terminals at a surface of the second microelectronic unit electrically coupled with (i) the one or more of the first unit contacts through first electrically conductive structure, and with (ii) the second chip contacts through second electrically conductive structure coupled with the second chip contacts.

2. The microelectronic package as claimed in claim 1 , wherein the first electrically conductive structure includes bond wires.

3. The microelectronic package as claimed in claim 1 , wherein the first microelectronic unit is configured to predominantly provide memory storage array function.

4. The microelectronic package as claimed in claim 3 , wherein the second microelectronic unit is configured to predominantly provide logic function.

5. The microelectronic package as claimed in claim 1 , wherein the first microelectronic unit further comprises a third semiconductor chip at least partially overlying the first semiconductor chip, the third semiconductor chip having third chip contacts positioned at a surface of the third semiconductor chip.

6. The microelectronic package as claimed in claim 5 , wherein at least one of the third chip contacts of third semiconductor chip is coupled to a second unit contact at the surface of the third semiconductor chip.

7. The microelectronic package as claimed in claim 5 , wherein at least some of the third chip contacts of the third semiconductor chip are disposed beyond an edge of the first semiconductor chip.

8. The microelectronic package as claimed in claim 5 , wherein the first chip contacts and the third chip contacts are disposed adjacent edges of the first and third semiconductor chips, respectively.

9. The microelectronic package as claimed in claim 2 , wherein at least some of the bond wires extend about an edge of the second microelectronic unit.

10. The microelectronic package as claimed in claim 2 , wherein at least some of the bond wires extend through a through opening in an encapsulant contacting an edge of the second semiconductor chip of the second microelectronic unit.

11. The microelectronic package as claimed in claim 10 , wherein at least some of the package terminals are disposed between the through opening and an edge of the second microelectronic unit.

12. The microelectronic package as claimed in claim 11 , wherein the at least some of the package terminals include at least one of power terminals or ground terminals.

13. The microelectronic package as claimed in claim 1 , wherein the first microelectronic unit is laterally offset from the second microelectronic unit.

14. The microelectronic package as claimed in claim 1 , wherein the first microelectronic unit is wider than the second microelectronic unit.

15. The microelectronic package as claimed in claim 1 , wherein at least one of the first or second microelectronic units is functionally testable in a state uncombined with the other of the first or second microelectronic units.

16. The microelectronic package as claimed in claim 1 , wherein each of the first or second microelectronic units is functionally testable in a state uncombined with the other of the first or second microelectronic units.

17. A microelectronic package comprising:

a first microelectronic unit including a first semiconductor chip having first chip contacts, the first microelectronic unit having first unit contacts positioned at a surface of the first microelectronic unit, the first unit contacts electrically coupled with the first chip contacts;

a second microelectronic unit including a second semiconductor chip having second chip contacts, the surface of the second semiconductor chip at least partially defining a face of the second microelectronic unit,

the first and second microelectronic units stacked without a substrate, such that one or more of the first unit contacts is positioned on a portion of the first microelectronic unit that extends beyond an edge of the second microelectronic unit; and

package terminals at the face of the second microelectronic unit electrically coupled with (i) the first unit contacts through first electrically conductive structure including bond wires, the bond wires extending above the face of the second microelectronic unit and laterally relative to the package terminals, and with (ii) the second chip contacts through second electrically conductive structure coupled with the second chip contacts, wherein at least some of the bond wires extend through a through the face of the second microelectronic unit.

18. The microelectronic package as claimed in claim 17 , wherein at least one of the first or second microelectronic units is functionally testable in a state of the at least one microelectronic unit uncombined with any the other of the first and second microelectronic units.

19. The microelectronic package as claimed in claim 18 , wherein the first microelectronic unit is laterally offset from the second microelectronic unit.

20. The microelectronic package as claimed in claim 19 , wherein the first microelectronic unit is wider than the second microelectronic unit.