Substrate-less stackable package with wire-bond interconnect
View Patent ↗A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.
1. An apparatus, comprising:
conductive elements of a conductive layer on a bottom side of a package;
wire bond wires coupled to and extending from first upper surface portions of the conductive elements;
a microelectronic element coupled to second upper surface portions of the conductive elements through conductive contact structures;
a wire bond wire of the wire bond wires interconnected for electrical conductivity to a conductive contact structure of the conductive contact structures by a conductive element of the conductive elements for a redistribution on the bottom side of the package; and
a dielectric layer contacting the wire bond wires and side portions of the microelectronic element to define at least one dimension of the package, the conductive layer at least partially defining the bottom side of the package.
2. The apparatus according to claim 1 , wherein the redistribution is configured to provide contacts of the package for interconnects for electrical conductivity with a microelectronic structure.
3. The apparatus according to claim 1 , wherein the redistribution is a lower redistribution, the apparatus further comprising a redistribution layer on an upper surface of dielectric layer interconnected for electrical conductivity to the wire bond wires for an upper redistribution on a top side of the package.
4. The apparatus according to claim 3 , wherein the lower redistribution and the upper redistribution respectively are configured for providing contacts of the package for interconnects for electrical conductivity with a first microelectronic structure and a second microelectronic structure.
5. The apparatus according to claim 4 , wherein the microelectronic element is in a face-down orientation.
6. The apparatus according to claim 4 , wherein the conductive elements are patterned from the conductive layer to define shapes of the conductive elements.
7. The apparatus according to claim 4 , wherein the wire bond wires are spaced away from a perimeter of the microelectronic element for the lower redistribution.
8. The apparatus according to claim 7 , wherein the redistribution layer extends over a backside surface of the microelectronic element for the upper redistribution.
9. The apparatus according to claim 8 , wherein the conductive contact structure includes a pad of the microelectronic element.
10. The apparatus according to claim 9 , wherein the conductive contact structure includes a solder mass.
11. The apparatus according to claim 10 , wherein the conductive contact structure includes a metalized via including the solder mass.
12. The apparatus according to claim 7 , wherein the conductive element is a trace.
13. The apparatus according to claim 3 , wherein the microelectronic element and the conductive contact structures respectively are a first microelectronic element and first conductive contact structures, the apparatus further comprising:
a second microelectronic element in a face-up orientation coupled over the first microelectronic element; and
the redistribution layer extending over the second microelectronic element and interconnected for electrical conductivity to the second microelectronic element through second conductive contact structures.
14. The apparatus according to claim 13 , wherein the second conductive contact structures include respective pads of the second microelectronic element.
15. The apparatus according to claim 14 , wherein the second conductive contact structures include respective solder masses.
16. The apparatus according to claim 13 , wherein the wire bond wires include coated cores.
17. The apparatus according to claim 3 , wherein the microelectronic element includes a first microelectronic element and a second microelectronic element in a stack.
18. The apparatus according to claim 17 , wherein the conductive contact structures are first conductive contact structures, the apparatus further comprising:
second conductive contact structures interconnected for electrical conductivity between the redistribution layer and the second microelectronic element.
19. The apparatus according to claim 18 , wherein:
the first microelectronic element is in a face-down orientation in the stack;
the second microelectronic element is in a face-up orientation and above the first microelectronic element in the stack; and
the redistribution layer extends over the second microelectronic element and is interconnected for electrical conductivity between the redistribution layer and the second microelectronic element through the second conductive contact structures.
20. The apparatus according to claim 19 , wherein the first and the second conductive contact structures include respective pads respectively of the first and the second microelectronic element.