Phase-locked loop circuit and delay-locked loop circuit
A phase-locked loop circuit includes a phase comparator that compares phases between a reference signal and a feedback signal and outputs a phase difference signal indicating a phase difference therebetween; a charge pump that outputs a charge pump current according to the phase difference signal; a low-pass filter that includes a resistor and a capacitor and that smoothes the charge pump current and converts the smoothed current into a control voltage; a voltage-controlled oscillator that generates an oscillation signal with a frequency according to the control voltage; and a frequency divider that generates a frequency-divided signal by frequency-dividing the oscillation signal and outputs the frequency-divided signal to the phase comparator as the feedback signal, wherein the resistor in the low-pass filter is a variable resistor that is changed according to the control voltage.
1. A delay-locked loop circuit comprising:
a phase comparator for comparing phases between a reference signal and a feedback signal and for outputting a phase difference signal indicating a phase difference therebetween;
a charge pump for outputting a charge pump current according to the phase difference signal;
a low-pass filter that includes a resistor and a capacitor, the low-pass filter smoothing the charge pump current and converting the smoothed current into a control voltage; and
a voltage-controlled delay device for generating a delay signal by providing an amount of delay according to the control voltage to the reference signal, and for outputting the delay signal to the phase comparator as the feedback signal,
wherein the resistor in the low-pass filter is a variable resistor that is changed according to the control voltage.
2. The delay-locked loop circuit according to claim 1 , wherein the variable resistor has a first field-effect transistor having a drain to which the control voltage is applied.
3. The delay-locked loop circuit according to claim 2 , wherein the voltage-controlled delay device has a load comprising a load field-effect transistor, and
the first field-effect transistor and the load field-effect transistor have a same channel length and a same channel width and have different numbers of parallel transistors.
4. The delay-locked loop circuit according to claim 2 , wherein a bias voltage is applied to a gate of the first field-effect transistor.
5. The delay-locked loop circuit according to claim 4 , further comprising a power supply voltage node and a reference potential node, wherein the first field-effect transistor is an n-channel field-effect transistor and is connected between a node of the control voltage and the reference potential node, and
the low-pass filter has a first capacitor connected between the power supply voltage node and the node of the control voltage.
6. The delay-locked loop circuit according to claim 5 , wherein the low-pass filter has a first capacitor connected in series with the first field-effect transistor and a second capacitor connected in series with the fixed resistor.
7. The delay-locked loop circuit according to claim 4 , further comprising a power supply voltage node and a reference potential node, wherein the first field-effect transistor is a p-channel field-effect transistor and is connected between a node of the control voltage and the power supply voltage node, and
the low-pass filter has a fixed resistor connected between the reference potential node and the node of the control voltage.
8. The delay-locked loop circuit according to claim 4 , wherein the variable resistor has a second field-effect transistor that is connected in parallel with the first field-effect transistor and is diode-connected.
9. The delay-locked loop circuit according to claim 8 , further comprising a reference potential node and a power supply voltage node, wherein the first field-effect transistor and the second field-effect transistor each are an n-channel field-effect transistor and are connected between a node of the control voltage and the reference potential node, and
the low-pass filter has a fixed resistor connected between the power supply voltage node and the node of the control voltage.
10. The delay-locked loop circuit according to claim 8 , further comprising a power supply voltage node and a reference potential node, wherein the first field-effect transistor and the second field-effect transistor each are a p-channel field-effect transistor and are connected between a node of the control voltage and the power supply voltage node, and
the low-pass filter has a fixed resistor connected between the reference potential node and the node of the control voltage.