Metal gate transistor and method for fabricating the same
View Patent ↗A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.
1. A method for fabricating metal gate transistor, comprising:
providing a substrate having a first transistor region and a second transistor region;
forming a stacked film on the substrate, wherein the stacked film comprises at least one high-k dielectric layer and a first metal layer;
patterning the stacked film to form a plurality of gates in the first transistor region and the second transistor region;
forming a dielectric layer on the gates;
planarizing a portion of the dielectric layer until reaching the top of each gate;
only removing the first metal layer from the gate of the second transistor region and keeping the first metal layer in the gate of the first transistor region; and
depositing a second metal layer over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.
2. The method of claim 1 , wherein the stacked film of the first transistor region further comprises a cap layer disposed between the high-k dielectric layer and the first metal layer.
3. The method of claim 2 , wherein the cap layer comprises LaO or Dy 2 O 3 .
4. The method of claim 1 , wherein the stacked film further comprises a sacrificial layer disposed on the first metal layer.
5. The method of claim 4 , wherein the sacrificial layer comprises a polysilicon layer.
6. The method of claim 4 , wherein the stacked film further comprises a hard mask disposed on the sacrificial layer.
7. The method of claim 4 , further comprising utilizing a dry etching process or a wet etching process to remove the sacrificial layer.
8. The method of claim 1 , wherein the high-k dielectric layer comprises HfSiO, HfSiON, HfO, LaO, LaAlO, ZrO, ZrSiO, or HfZrO.
9. The method of claim 1 , wherein the first transistor region is a NMOS transistor region.
10. The method of claim 9 , wherein the first metal layer comprises TiN, TaC, Ta, TaSiN, Al, or TiAlN.
11. The method of claim 1 , wherein the second transistor region comprises a PMOS transistor region.
12. The method of claim 11 , wherein the second metal layer comprises TiN, W, WN, Pt, Ni, Ru, TaCN, or TaCNO.
13. The method of claim 1 , further comprising forming a spacer on the sidewall of each gate.
14. The method of claim 13 , further comprising forming a source/drain region in the first transistor region and the second transistor region after forming the spacer and before forming the dielectric layer.
15. The method of claim 1 , further comprising forming a patterned photoresist in the first transistor region before removing the first metal layer from the gate of the second transistor region.
16. The method of claim 1 , further comprising forming a low resistance conductive layer on the second metal layer.