Method Of Programming A Nonvolatile Memory Device

1 . A method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data, the method comprising:

performing a least significant bit (LSB) program operation that programs LSBs of the multi-bit data in the plurality of multi-level cells; and

performing a most significant bit (MSB) program operation that programs MSBs of the multi-bit data in the plurality of multi-level cells, wherein performing the MSB program operation includes

performing an MSB pre-program operation on first multi-level cells from among the plurality of multi-level cells that are to be programmed to a highest target program state among a plurality of target program states; and

performing an MSB main program operation that programs the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.

2 . The method of claim 1 , wherein performing the MSB pre-program operation comprises:

programming the first multi-level cells to an intermediate program state corresponding to the highest target program state by applying a one-shot pulse to the first multi-level cells.

3 . The method of claim 1 , wherein performing the MSB pre-program operation comprises:

applying an incremental step pulse to the first multi-level cells; and

applying a pre-program verify voltage to the first multi-level cells to verify whether the first multi-level cells are programmed to an intermediate program state corresponding to the highest target program state.

4 . The method of claim 1 , wherein performing the MSB pre-program operation comprises:

programming the first multi-level cells to a first intermediate program state corresponding to the highest target program state;

dividing the first intermediate program state into a plurality of sections; and

programming the first multi-level cells to a second intermediate program state narrower than the first intermediate program state by, for each of the first multi-level cells, increasing a threshold voltage of the first multi-level cell by one of a plurality of different voltage amounts based on which of the plurality of sections the first multi-level cell corresponds to.

5 . The method of claim 4 , wherein programming the first multi-level cells to the first intermediate program state comprises:

applying a first one-shot pulse to the first multi-level cells.

6 . The method of claim 4 , wherein dividing the first intermediate program state into the plurality of sections comprises:

applying at least one division voltage to the first multi-level cells to determine which of the plurality of sections each first multi-level cell exists in.

7 . The method of claim 4 , wherein the plurality of sections include a first section, a second section and a third section, and wherein programming the first multi-level cells to the second intermediate program state includes

applying a first voltage of low level to bitlines coupled to the first multi-level cells in the first section;

applying a forcing voltage to bitlines coupled to the first multi-level cells in the second section;

applying a second voltage of high level to bitlines coupled to the first multi-level cells in the third section; and

applying a second one-shot pulse to a selected wordline coupled to the first multi-level cells.

8 . The method of claim 7 , wherein the first voltage is a low power supply voltage, the second voltage is a high power supply voltage, and the forcing voltage has a voltage level higher than that of the first voltage and lower than that of the second voltage.

9 . The method of claim 7 , wherein, the second one-shot pulse is applied to the selected wordline such that threshold voltages of the first multi-level cells in the third section are not substantially increased, and increments of threshold voltages of the first multi-level cells in the second section are smaller than increments of threshold voltages of the first multi-level cells in the first section.

10 . A method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data, the method comprising:

performing a least significant bit (LSB) program operation that programs LSBs of the multi-bit data in the plurality of multi-level cells; and

performing a most significant bit (MSB) program operation that programs MSBs of the multi-bit data in the multi-level cells, wherein performing the MSB program operation includes

performing an MSB pre-program operation on first multi-level cells from among the plurality of multi-level cells that are to be programmed to at least one target program state among a plurality of target program states; and

performing an MSB main program operation that programs the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.

11 . The method of claim 10 , wherein the at least one target program state includes a highest target program state among the plurality of target program states.

12 . The method of claim 10 , wherein the at least one target program state includes all the plurality of target program states.

13 . The method of claim 12 , wherein performing the MSB pre-program operation comprises:

programming the plurality of multi-level cells to a plurality of intermediate program states corresponding to the plurality of target program states by sequentially applying a plurality of one-shot pulses respectively corresponding to the plurality of intermediate program states to the plurality of multi-level cells.

14 . The method of claim 12 , wherein performing the MSB pre-program operation comprises:

applying an incremental step pulse to the multi-level cells; and

sequentially applying a plurality of pre-program verify voltages to the plurality of multi-level cells to verify whether the multi-level cells are programmed to a plurality of intermediate program states respectively corresponding to the plurality of target program states.

15 . The method of claim 12 , wherein performing the MSB pre-program operation comprises:

programming the plurality of multi-level cells to a first plurality of intermediate program states respectively corresponding to the plurality of target program states;

dividing each of the first plurality of intermediate program states into a plurality of sections; and

programming the plurality of multi-level cells to a second plurality of intermediate program states respectively narrower than the first plurality of intermediate program states by increasing threshold voltages of the plurality of multi-level cells by different voltage levels according to the plurality of sections.

16 . A method of programming multi-bit data in a plurality of multi-level cells of a nonvolatile memory device, the method comprising:

programming least significant bits (LSBs) of the multi-bit data in the multi-level cells; and

programming most significant bits (MSBs) of the multi-bit data in the plurality of multi-level cells, for each of the plurality of multi-level cells, by verifying a threshold voltage of the multi-level cell using a verification voltage of a target voltage level, from among a plurality of target voltage levels, corresponding to the multi-level cell, wherein programming the MSBs includes

performing a MSB pre-program operation, for each of first multi-level cells from among the plurality of multi-level cells, by verifying a threshold voltage of the first multi-level cell using a verification voltage of an intermediate voltage level corresponding to the first multi-level cell, the corresponding intermediate voltage level being lower than the corresponding target voltage level; and

after performing the MSB pre-program operation, performing an MSB main program operation, for each of the plurality of multi-level cells, by verifying a threshold voltage of the multi-level cell using the verification voltage of the target voltage level that corresponds to the multi-level cell.

17 . A method of programming multi-bit data in a plurality of multi-level cells of a nonvolatile memory device, the method comprising:

programming least significant bits (LSBs) of the multi-bit data in the multi-level cells;

performing a most significant bit (MSB) pre-program operation by, for each of first multi-level cells from among the plurality of multi-level cells

applying a first programming pulse to the first multi-level cell,

determining a threshold voltage region, from among a plurality of threshold voltage regions, to which the first multi-level cell belongs, and

applying, to the first multi-level cell, a second programming pulse having a voltage level selected from among a plurality of different voltage levels based on the region from among the plurality of regions to which the first multi-level cell corresponds; and

after performing the MSB pre-program operation, programming MSBs of the multi-bit data in the multi-level cells.