Fabrication of graphene electronic devices using step surface contour
A method for fabricating an electronic component, comprising providing a substrate; and depositing a graphene layer; wherein the substrate is either provided with a van-der-Waals functional layer or a van-der-Waals functional layer is deposited on the substrate before depositing the graphene layer; a surface step contour is formed; and growth of the graphene layer is seeded at the step contour.
1. A method for fabricating an electronic component, comprising:
providing a substrate and a plurality of surface step contours on the substrate; and
depositing a van der Waals layer adjacent to the surface step contours; and
depositing a graphene layer on the van der Waals layer; wherein
growth of the graphene layer is seeded at a kink of the surface step contours.
2. The method according to claim 1 , wherein forming the surface step-contours comprises fabricating a line-shaped or mesa-shaped seed layer on the van-der-Waals functional layer.
3. The method according to claim 2 , wherein the seed layer is made of Si or a metal from the group formed by Ti, Ni, Al, and Cu.
4. The method according to claim 1 , wherein providing the surface step contours comprises a depositing a plurality of seed layers, which are stacked in a vertical direction on the surface and are separated from each other by a respective intermediate dielectric layer.
5. The method according to claim 1 , wherein a forming the surface step contours comprises fabricating the surface step contour to have a step-height that limits a vertical growth of the graphene layer to a monolayer or a bi-layer of graphene.
6. The method according to claim 1 , wherein the substrate either contains or consists of silicon.
7. The method according to claim 1 , wherein depositing the graphene layer is performed at a substrate temperature higher than 600° C. and lower than 1000° C.
8. The method according to claim 1 , wherein depositing the graphene layer comprises depositing atomic Carbon (C).
9. The method according to claim 1 , wherein depositing the graphene layer comprises catalytically separating Carbon atoms (C) from a Carbon-comprising compound.
10. An electronic component comprising:
a substrate and a plurality of surface step contours on the substrate;
a van-der-Waals layer deposited adjacent to the step contours; and,
a graphene layer on the van der Waals layer and seeded at a kink of the step contours.
11. The electronic component according to claim 10 , comprising a plurality of graphene layers, which are arranged in a lateral layer sequence or in a vertical layer stack.
12. The electronic component of claim 10 , which takes the form of a memory cell or a transistor.
13. The electronic component of claim 10 , wherein a line-shaped or mesa-shaped seed layer is arranged between the van-der-Waals layer and the graphene layer.
14. The electronic component of claim 10 , wherein the substrate either contains or consists of silicon.
15. The electronic component of claim 10 , wherein the van-der-Waals functional layer is made from the group formed by boron nitride BN and aluminum oxide Al 2 O 3 .