Multi-core decompression of block coded video data
View Patent ↗Apparatus for and a method of decompression of block coded video data in a multi-core processor. The processor cores decode respective coded groups of blocks of video data independently, in parallel and deblock respective decoded groups of blocks of video data independently and in parallel with the decode operations and with other deblock operations.
1. An apparatus for multi-core decompression of block coded video data, comprising:
a plurality of processor cores; and
a task management module, connected to said processor cores, that controls said processor cores to decode respective coded groups of blocks of video data independently in parallel and to deblock respective decoded groups of blocks of video data independently in parallel,
wherein:
any of said processor cores can perform decoding and deblocking,
any of said processor cores can perform both slice decoding and deblocking to reduce decoding latency, and
multiple decode and multiple deblock tasks are performed in parallel, and
wherein, in order to detect lost packets, said task management module verifies whether more packets are available to be processed, verifies whether available packets are from a current access unit and, if one core is in a WAITING state and all the other cores are in a TERMINATE state, said task management module verifies whether all packets of the current access unit have been successfully decoded with no packet loss detection.
2. The apparatus of claim 1 , wherein each of said coded groups of blocks of video data is a slice of a video frame that is coded separately from other slices of video data and said task management module controls said processor cores to decode respective coded slices of video data independently in parallel.
3. The apparatus of claim 1 , wherein said task management module controls at least one of said processor cores to deblock one or more decoded groups of blocks of video data independently in parallel with at least one other of said processor cores decoding one or more of said coded groups of blocks of video data.
4. The apparatus of claim 1 , wherein said task management module controls said processor cores to decode respective coded groups of blocks with equal weighting, and to deblock respective decoded groups of blocks of video data subject to dependencies.
5. The apparatus of claim 1 , wherein said task management module merges a plurality of deblock tasks and controls at least one of said processor cores to perform the merged tasks.
6. The apparatus of claim 1 , further comprising a non-cacheable memory that is shared by said processor cores for task management buffers, core states and inter-core communication controlling messages.
7. The apparatus of claim 1 , further comprising a shared memory that is cacheable in said processor cores for reference pictures, currently decoded pictures, deblocking filter parameters, motion vectors and reference picture list buffers, wherein said processor cores include respective local cacheable memories for current coding parameters and pointers to shared cacheable and shared non-cacheable memories.
8. The apparatus of claim 7 , wherein one of said processor cores initializes said reference picture lists and performs memory management control operations for a new video access unit, and the initialized reference picture lists are copied locally by the others of said processor cores, which re-order the locally copied reference picture lists independently.
9. The apparatus of claim 1 , wherein said processor cores verify whether a packet received from said task management module is from a current access unit, decode the packet if it is from the current access unit, and signal to said task management module if the packet is not from the current access unit.
10. A method of decompression of block coded video data in a multi-core processor comprising a plurality of processor cores, the method comprising:
controlling said processor cores to decode respective coded groups of blocks of video data independently in parallel; and
controlling said processor cores to deblock respective decoded groups of blocks of video data independently in parallel
wherein:
any of said processor cores can perform both decoding and deblocking,
any of said processor cores can perform both slice decoding and deblocking to reduce decoding latency, and
multiple decode and multiple deblock tasks are performed in parallel, and
wherein detecting lost packets includes verifying whether more packets are available to be processed, verifying whether available packets are from a current access unit and, if one of said cores is in a WAITING state and all the others are in a TERMINATE state, verifying whether all packets of the current access unit have been successfully decoded with no packet loss detection.
11. The method of claim 10 , wherein each of said coded groups of blocks of video data is a slice of a video frame that is coded separately from other slices and said processor cores decode respective coded slices of video data independently in parallel.
12. The method of claim 10 , wherein at least one of said processor cores deblocks one or more decoded groups of blocks of video data independently in parallel with at least one other of said processor cores decoding one or more of said coded groups of blocks of video data.
13. The method of claim 10 , wherein said processor cores decode respective coded groups of blocks with equal weighting, and deblock respective decoded groups of blocks of video data subject to dependencies.
14. The method of claim 10 , wherein a plurality of deblock tasks are merged and at least one of said processor cores performs the merged tasks.
15. The method of claim 10 , wherein said processor cores share a non-cacheable memory for task management buffers, core states and inter-core communication controlling messages.
16. The method of claim 10 , wherein said processor cores share a memory that is cacheable for reference pictures, currently decoded picture, deblocking filter parameters, motion vectors and reference picture list buffers, and wherein said processor cores include respective local cacheable memories for current coding parameters and pointers to shared cacheable and shared non-cacheable memories.
17. The method of claim 16 , wherein one of said processor cores initializes said reference picture lists and performs memory management control operations for a new video access unit, and the initialized reference picture lists are copied locally by other processor cores, which re-order the locally copied reference picture lists independently.
18. The method of claim 10 , wherein said processor cores verify whether a packet received from said task management module is from a current access unit, decode the packet if it is from the current access unit, and signal to said task management module if the packet is not from the current access unit.