PLL

1. A Phase Lock Loop (PLL) comprising:

A phase comparator which compares phases of a reference clock and a feedback clock and outputs phase-difference signal;

a charge-pump equalizer, which includes a plurality of charge pumps, the plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds the charge currents generated by the plurality of charge pumps, and outputs the added charge current;

a loop filter which generates a control voltage according to the charge current;

a voltage controlled oscillator which generates an output clock having a frequency corresponding to the control voltage;

a divider which divides the output clock to generate the feedback clock;

a replica circuit, which includes a digital filter, the digital filter having ideal characteristics of the loop filter and the voltage controlled oscillator, inputting in a phase-difference digital value having phase difference of the phase-difference signal, and generating a replica output according to the ideal characteristics, and outputs a difference signal based on the replica output and an ideal value; and

a coefficient generating circuit which smoothes correlation values of the difference signal and the phase-difference signal to generate charge pump coefficients, and negatively feeds back the charge pump coefficients to the plurality of charge pumps respectively, wherein the plurality of charge pumps generate the charge currents each having current value corresponding to each of the charge pump coefficients.

2. The PLL according to claim 1 , wherein

the phase-difference signal includes a first phase-difference signal, which has a first value for the time of the phase difference, in a first case that phase of the reference clock leads or retards behind phase of the feedback clock, and a second phase-difference signal, which has a second value for the time of the phase difference, in a second case which is opposite to the first case,

each of the plurality of the charge pumps in the charge-pump equalizer includes a first charge pump which generates a positive charge current according to the first phase-difference signal and a second charge pump which generates a negative charge current according to the second phase-difference signal, and

the charge-pump equalizer adds and outputs the positive and negative charge currents of the plurality of the charge pumps.

3. The PLL according to claim 2 , wherein

the coefficient generating circuit includes a correlation value generating circuit for generating the correlation values corresponding to correlation between the difference signal and the phase-difference signal at a corresponding time thereto.

4. The PLL according to claim 3 , wherein

the correlation value generating circuit includes a plurality of first and second multipliers each of which multiples the difference signal and the phase-difference signal at a corresponding time thereto, and a plurality of first and second smoothing circuits each of which respectively smoothes outputs of the first and the second multipliers, with respect to the plurality of the first and the second charge pumps of the plurality of the charge pumps, and

outputs of the plurality of the first and the second smoothing circuits are respectively negatively fed back, as weighting coefficients, to the plurality of the first and the second charge pumps.

5. The PLL according to claim 4 , further comprising:

a first delay circuit which delays the phase-difference signal and provides phase-difference signals with different delay times respectively to the plurality of the charge pumps, and

a second delay circuit which delays the phase-difference signals with the different delay times by delay time of the replica circuit and provides the same to the plurality of the first and the second multipliers.

6. The PLL according to claim 4 , wherein

each of the first and the second smoothing circuits multiplies the outputs of the multipliers by an attenuation coefficient and integrates the multiplied values.

7. The PLL according to claim 2 , wherein

the replica circuit further includes an integrator which integrates a first value of the first phase-difference signal and a second value of the second phase-difference signal in sync with an over-sample clock to generate the phase difference digital value, and a difference circuit which generates the difference signal between the replica output and the ideal output.

8. The PLL according to claim 1 , wherein

the digital filter includes a FIR filter having a plurality of filter multipliers which multiply a plurality of delay input signals, which are obtained by delaying input signals by different times, by tap coefficients respectively, and an adder, which adds outputs of the plurality of filter multipliers.

9. The PLL according to claim 2 , wherein

the first charge pump includes a PMOS transistor which is connected to a power supply voltage and generates the positive charge current,

the second charge pump includes a NMOS transistor which is connected to a ground and generates the negative charge current, and

in each of the plurality of the charge pumps, the PMOS transistor and the NMOS transistor is connected so that the positive and the negative charge currents are added.

10. The PLL according to claim 2 , wherein

the loop filter includes a CR filter which integrates the added charge currents.

11. The PLL according to claim 2 , wherein the voltage controlled oscillator includes an LC oscillator, of which a capacitance is variably controlled according to the control voltage.