Reset signal distribution
Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. One or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.
1. A method comprising:
receiving a reset signal to be synchronously distributed via a plurality of pipelined reset blocks to a plurality of ports of a core circuit;
transmitting the reset signal successively to at least some of the plurality of pipelined reset blocks to provide delayed reset signals having delay times based on locations of the at least some of the pipelined reset blocks; and
programmably coupling at least one of the delayed reset signals to at least one of the plurality of ports of the core circuit.
2. The method of claim 1 , further comprising synchronizing the reset signal, at an input reset block, with one of a plurality of clock signals.
3. The method of claim 1 , further comprising distributing the reset signal to the core circuit, the core circuit comprising an asynchronous circuit surrounded by a reset circuit that includes at least some of the pipelined reset blocks.
4. The method of claim 1 , further comprising programmably adjusting the delay times so that the delayed reset signals distributed to the plurality of ports of the core circuit have substantially balanced reset de-assertion latencies.
5. The method of claim 1 , further comprising programmably adjusting the delay times by setting an Nth delay time at an Nth one of the pipelined reset blocks less than a first delay time at a first one of the pipelined reset blocks, where N is an integer greater than 1.
6. The method of claim 1 , further comprising adjusting at least one of the delay times based on a distance between a first one of the pipelined reset blocks and a second one of the pipelined reset blocks.
7. The method of claim 1 , further comprising synchronizing the received reset signal with a clock signal with which the reset signal was previously synchronized at an input reset block.
8. A machine-readable medium comprising instructions, which when executed by a machine, perform a method, the method comprising:
receiving a reset signal to be synchronously distributed via a plurality of pipelined reset blocks to a plurality of ports of a core circuit;
transmitting the reset signal successively to at least some of the plurality of pipelined reset blocks to provide delayed reset signals having delay times based on locations of the at least some of the pipelined reset blocks; and
programmably coupling at least one of the delayed reset signals to at least one of the plurality of ports of the core circuit.
9. The machine-readable medium of claim 8 , wherein programmably coupling comprises:
programmably coupling the delayed reset signals to a plurality of input/output ports of a plurality of banks of the core circuit.
10. The machine-readable medium of claim 8 , wherein the method further comprises:
resynchronizing the received reset signal in at least some of the plurality of pipelined reset blocks with one of a plurality of clock signals.
11. An integrated circuit comprising:
a plurality of pipelined reset blocks to distribute a reset signal to a plurality of ports of a core circuit, wherein at least some of the plurality of pipelined reset blocks are configured to receive and transmit the reset signal successively to a next one of the plurality of pipelined reset blocks and to provide delayed reset signals having delay times based on locations of the at least some of the pipelined reset blocks, at least one of the delayed reset signals to be programmably coupled to at least one of the plurality of ports of the core circuit.
12. The integrated circuit of claim 11 , further comprising:
at least one reset input block to generate the reset signal, the at least one input block comprising a pair of multiplexers to receive input signals and to select a clock signal.
13. The integrated circuit of claim 11 , wherein at least one of the plurality of pipelined reset blocks comprise a pipelined counter to adjust at least one of the delay times.
14. The integrated circuit of claim 13 , wherein the pipelined counter is configured to programmably adjust the at least one of the delay times.
15. The integrated circuit of claim 14 , wherein the programmably adjusting the at least one of the delay times comprises setting an Nth delay time at an Nth one of the pipelined reset blocks approximately N times smaller than a first delay time at a first one of the pipelined reset blocks.
16. The integrated circuit of claim 11 , wherein the delay times are adjusted so that the delayed reset signals distributed to the plurality of ports of the core circuit have substantially balanced reset de-assertion latencies.
17. The integrated circuit of claim 11 , wherein the pipelined reset blocks are located at approximately equal distances from each other.
18. The integrated circuit of claim 11 , wherein at least one of the pipelined reset blocks further comprises:
a synchronizer to synchronize a received version of the reset signal with a clock signal selected by a multiplexer included in the at least one of the pipelined reset blocks.
19. The integrated circuit of claim 11 , wherein at least one of the delay times is determined based on a distance between a first one of the pipelined reset blocks and a second one of the pipelined reset blocks.
20. The integrated circuit of claim 11 , wherein the core circuit comprises:
an asynchronous circuit surrounded by a reset circuit that includes at least some of the plurality of pipelined reset blocks.