Metal gate features of semiconductor die
View Patent ↗A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio.
1. A CMOS semiconductor die comprising:
a substrate;
an insulation layer over a major surface of the substrate;
a plurality of P-metal gate areas within the insulation layer collectively covering a first area of the major surface within a first device region over the major surface;
a plurality of N-metal gate areas within the insulation layer collectively covering a second area of the major surface within the first device region;
a plurality of dummy P-metal gate areas within the insulation layer collectively covering a third area of the major surface within a second device region over the major surface; and
a plurality of dummy N-metal gate areas within the insulation layer collectively covering a fourth area of the major surface within the second device region;
wherein the N-metal gate areas of the plurality of N-metal gate areas within the first device region individually differ in size compared to the P-metal gate areas of the plurality P-metal gate areas within the first device region, and the dummy P-metal gate areas of the plurality of dummy P-metal gate areas within the second device region are individually uniform in size with respect to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas within the second device region.
2. The CMOS semiconductor die of claim 1 , wherein a first ratio of the first area to the second area is from 1 to 3.
3. The CMOS semiconductor die of claim 2 , wherein a second ratio of the third area to the fourth area is from 1 to 3.
4. The CMOS semiconductor die of claim 1 , wherein the dummy P-metal gate areas of the plurality of dummy P-metal gate areas are similar in shape with respect to one another.
5. The CMOS semiconductor die of claim 1 , wherein the dummy N-metal gate areas of the plurality of dummy N-metal gate areas are similar in shape with respect to one another.
6. The CMOS semiconductor die of claim 1 , wherein the dummy P-metal gate areas of the plurality of dummy P-metal gate areas have a similar shape compared to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas.
7. The CMOS semiconductor die of claim 1 , wherein one dummy N-metal gate area of the plurality of dummy N-metal gate areas is between two dummy P-metal gate areas of the plurality of dummy P-metal gate areas.
8. The CMOS semiconductor die of claim 1 , wherein one dummy P-metal gate area of the plurality of dummy P-metal gate areas is between two dummy N-metal gate areas of the plurality of dummy N-metal gate areas.
9. The CMOS semiconductor die of claim 1 , wherein one dummy N-metal gate area of the plurality of dummy N-metal gate areas is between one dummy P-metal gate area of the plurality of dummy P-metal gate areas and one P-metal gate area of the plurality of P-metal gate areas.
10. The CMOS semiconductor die of claim 1 , wherein one dummy P-metal gate area of the plurality of dummy P-metal gate areas is between one dummy N-metal gate area of the plurality of dummy N-metal gate areas and one N-metal gate area of the plurality of N-metal gate areas.
11. The CMOS semiconductor die of claim 1 , wherein the dummy P-metal gate areas of the plurality of dummy P-metal gate areas comprise one or more of TiN, WN, TaN, or Ru.
12. The CMOS semiconductor die of claim 1 , wherein the dummy N-metal gate areas of the plurality of dummy N-metal gate areas comprise one or more of Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.
13. The CMOS semiconductor die of claim 3 , further comprising:
a plurality of resistor areas within the insulation layer collectively covering a fifth area of the major surface;
a plurality of resistor contacts within the insulation layer; and
a plurality of dummy resistor areas formed within the insulation layer collectively covering a sixth area of the major surface,
wherein the resistor areas of the plurality of resistor areas comprise poly-silicon, and the resistor contacts of the plurality of resistor contacts comprise a third metal material.
14. The CMOS semiconductor die of claim 13 , wherein a third ratio of the fifth area to a sum of the first area and second area is less than 0.05.
15. The CMOS semiconductor die of claim 14 , wherein a fourth ratio of the sixth area to a sum of the third area and fourth area is less than 0.05.
16. The CMOS semiconductor die of claim 13 , wherein the dummy resistor areas of the plurality of dummy resistor areas comprise poly-silicon.
17. A CMOS semiconductor die comprising:
a substrate;
an insulation layer over a major surface of the substrate;
a plurality of P-metal gate areas within the insulation layer collectively covering a first area of the major surface within a first device region over the major surface;
a plurality of N-metal gate areas within the insulation layer collectively covering a second area of the major surface within the first device region;
a plurality of dummy P-metal gate areas within the insulation layer collectively covering a third area of the major surface within a second device region over the major surface; and
a plurality of dummy N-metal gate areas within the insulation layer collectively covering a fourth area of the major surface within the second device region,
wherein a first ratio of the first area to the second area is equal to or greater than 1 , and a second ratio of the third area to the fourth area is substantially equal to the first ratio.
18. The CMOS semiconductor die of claim 17 , wherein the N-metal gate areas of the plurality of N-metal gate areas within the first device region individually differ in shape compared to the P-metal gate areas of the plurality P-metal gate areas within the first device region, and the dummy P-metal gate areas of the plurality of dummy P-metal gate areas within the second device region are individually uniform in shape with respect to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas within the second device region.
19. A CMOS semiconductor die comprising:
a substrate;
a plurality of P-metal gate areas over the substrate within a first device region;
a plurality of N-metal gate areas over substrate within the first device region;
a plurality of dummy P-metal gate areas over the substrate within a second device region, the second device region being different from the first device region; and
a plurality of dummy N-metal gate areas over the substrate within the second device region;
wherein a surface area of the first device region is larger than the second device region, N-metal gate areas of the plurality of N-metal gate areas within the first device region individually differ in size compared to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas within the second device region, and the P-metal gate areas of the plurality P-metal gate areas within the first device region individually differ in size compared to the dummy P-metal gate areas of the plurality of dummy P-metal gate areas within the second device region.
20. The CMOS semiconductor die of claim 19 , wherein the dummy P-metal gate areas of the plurality of dummy P-metal gate areas within the second device region are individually uniform in size with respect to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas within the second device region.