Resistance variable memory cell
View Patent ↗Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various other benefits. One or more embodiments can reduce the number of processing steps associated with providing local interconnects to phase change memory arrays.
1. A resistance variable memory cell, comprising:
a stack structure including a resistance variable material formed between a first electrode and a second electrode;
a heat sink comprised of a thermally conductive material located between a stack structure associated with an adjacent resistance variable memory cell; and
a dielectric material formed on a first sidewall of the stack structure and on a first sidewall of the stack structure associated with the adjacent resistance variable memory cell;
wherein the dielectric material is a continuous encapsulation layer formed over the stack structure and the stack structure associated with the adjacent resistance variable memory cell; and
wherein the heat sink is located in a gap formed by the continuous encapsulation layer.
2. The memory cell of claim 1 , wherein a thermal conductivity of the thermally conductive material is at least 30 W/m·K.
3. The memory cell of claim 1 , wherein a thermal conductivity of the thermally conductive material is at least 100 W/m·K.
4. The memory cell of claim 1 , wherein the heat sink is comprised of a metal.
5. The memory cell of claim 1 , wherein the resistance variable material is a phase change material.
6. The memory cell of claim 5 , wherein the resistance variable material contacts the first and the second electrode.
7. A resistance variable memory cell, comprising:
a first, a second, and a third metal contact formed on a substrate, the third metal contact located between the first and second metal contact;
a first stack structure formed a distance from a second stack structure, the first and the second stack structures including a resistance variable material formed between a first electrode and a second electrode, wherein the first electrode of the first stack is coupled to the first metal contact and the first electrode of the second stack is coupled to the second metal contact;
a continuous encapsulation layer formed over the first and second stack structures, the continuous encapsulation layer comprising a dielectric material formed on a wall of the first and the second stack structure and over the third metal contact; and
a heat sink material formed in a gap formed by the continuous encapsulation layer between the first stack structure and the second stack structure.
8. The memory cell of claim 7 , wherein the heat sink material is formed over at least a portion of the third metal contact.
9. The memory cell of claim 7 , wherein the first electrode is a bottom electrode and the second electrode is a top electrode.
10. The memory cell of claim 7 , wherein at least one of the first and the second metal contact is a drain contact coupled to a drain region associated with the substrate.
11. The memory cell of claim 7 , wherein the third metal contact is a source contact coupled to a source region associated with the substrate.
12. The memory cell of claim 7 , including a gate of an access transistor formed between the first and the third metal contact.
13. A resistance variable memory cell, comprising:
a first stack structure comprising a resistance variable material formed between a bottom electrode and a top electrode;
a first metal contact coupled to the bottom electrode and to an access device corresponding to the memory cell;
a heat sink material located between the first stack structure and a second stack structure corresponding to an adjacent resistance variable memory cell; and
a dielectric material formed on a first sidewall of the first stack structure and on a first sidewall of the second stack structure;
wherein the dielectric material is a continuous encapsulation layer formed over the first stack structure and the second stack structure; and
wherein the heat sink is located in a gap formed by the continuous encapsulation layer.