Differential signal termination circuit
View Patent ↗A multi-mode differential termination circuit has a pair of differential input terminals for receiving external differential signals, a pair of series-connected load elements coupled between said differential input terminals, and an analog interface terminal coupled a common junction point of said load elements. A bias circuit is coupled to the common junction point of the load elements for selectively applying a bias voltage thereto in response to a digital control signal. A control input receives the digital control signal to activate the bias circuit.
1. A multi-mode differential termination circuit, comprising:
a pair of differential input terminals for receiving external differential signals;
a pair of series-connected load elements coupled between said differential input terminals;
an analog interface terminal coupled to a common junction point of said load elements;
a bias circuit coupled to the common junction point of said load elements for selectively applying a bias voltage thereto in response to a digital control signal; and
a control input for receiving the digital control signal to activate the bias circuit,
wherein the bias circuit comprises a pair of series-connected resistive elements, and a pair of digital switches operated by said digital control signal to connect said respective resistive elements to voltage supply rails.
2. A multi-mode differential termination circuit as claimed in claim 1 , wherein the digital switches are field effect transistors.
3. A multi-mode differential termination circuit as claimed in claim 2 , wherein one of said field effect transistors is an NMOS transistor and the other of said transistors is a PMOS transistor.
4. A multi-mode differential termination circuit as claimed in claim 1 , wherein in the default state of the control pin, the digital switches are turned off, and the application of the digital control signal turns the digital switches on.
5. A multi-mode differential termination circuit as claimed in claim 1 , wherein the load elements are resistors.
6. A multi-mode differential termination circuit as claimed in claim 1 , wherein the control input is connected to one of the digital switches via a buffer amplifier.
7. A multi-mode differential termination circuit as claimed in claim 1 , wherein the components of the circuit are integrated onto a single chip.
8. A multi-mode differential termination circuit, comprising:
a pair of differential input terminals for receiving external differential signals;
a pair of series-connected load elements coupled between said differential input terminals;
an analog interface terminal coupled to a common junction point of said load elements;
a bias circuit coupled to the common junction point of said load elements for selectively applying a bias voltage thereto in response to a digital control signal; and
a control input for receiving the digital control signal to activate the bias circuit,
wherein the analog interface terminal is coupled to the common junction point of said load elements by a resistor.
9. A multi-mode differential termination circuit as claimed in claim 8 , wherein the bias circuit is coupled to the common junction point by said resistor.
10. A method of terminating a differential signal, comprising:
applying the differential signal to a pair of differential input terminals having a pair of series-connected load elements coupled between them; and
determining the mode of operation by setting an analog condition of an analog interface terminal coupled to a common junction point of said load elements and a digital condition of a control input for activating a bias circuit coupled to the common junction point of said load elements,
wherein the bias circuit comprises a pair of series-connected resistive elements, and the state of a pair of digital switches operative to connect the resistive elements to the respective supply rails is determined by the digital condition of the control input.
11. A method as claimed in claim 10 , wherein the digital switches are field effect transistors.
12. A method as claimed in claim 11 , wherein one of said field effect transistors is an NMOS transistor and the other of said transistors is a P MOS transistor.
13. A method as claimed in claim 10 , wherein in the default state, the digital switches are turned off, and the application of the digital control signal to the control pin turns the digital switches on.
14. A method as claimed in claim 10 , wherein the load elements are resistors.
15. A method as claimed in claim 10 , wherein in a direct coupled PECL mode, the analog interface terminal is connected to ground and the control input is configured to inactivate the bias circuit.
16. A method as claimed in claim 10 , wherein in an AC coupled PECL mode, analog interface terminal is open and the control input is configured to activate the bias circuit, and the control signals are applied to the input terminals via capacitors.
17. A method as claimed in claim 10 , wherein in a direct coupled LVDS mode, the analog interface terminal is open and the control input is configured to inactivate the bias circuit.
18. A method as claimed in claim 10 , wherein in an AC coupled LVDS mode, the analog interface terminal is open and the control input is configured to activate the bias circuit.
19. A method of terminating a differential signal, comprising:
applying the differential signal to a pair of differential input terminals having a pair of series-connected load elements coupled between said them; and
determining the mode of operation by setting an analog condition of an analog interface terminal coupled to a common junction point of said load elements and a digital condition of a control input for activating a bias circuit coupled to the common junction point of said load elements,
wherein the analog interface terminal is coupled to the common junction point of said load elements by a resistor.
20. A method as claimed in claim 19 , wherein the bias circuit is coupled to the common junction point by said resistor.