Semiconductor phast change memory using multiple phase change layers
View Patent ↗In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
1. A method of operating a phase change memory comprising:
providing a phase change memory, said phase change memory including a first electrode, a second electrode, a first phase change layer between said first and second electrodes, a second phase change layer between said first and second electrodes, and a third phase change layer between said first and second electrodes; and
applying a voltage between said first and second electrodes, said voltage inducing passage of a current from said first electrode to said second electrode, said current inducing interdiffusion of said first and second phase change layers without inducing interdiffusion of said third phase change layer with either said first phase change layer or said second phase change layer.
2. The method of claim 1 wherein said second phase change layer is between said first phase change layer and said third phase change layer.
3. The method of claim 1 wherein said first phase change layer contacts said second phase change layer.
4. The method of claim 3 wherein said third phase change layer contacts said first phase change layer.
5. The method of claim 1 wherein said current induces melting of said first phase change layer.
6. The method of claim 5 wherein said current induces melting of said second phase change layer.
7. The method of claim 1 wherein said interdiffusion causes said first phase change layer to react with said second phase change layer.
8. The method of claim 1 wherein said phase change memory further includes a fourth phase change layer, said current inducing interdiffusion of said fourth phase change layer with at least one of said first phase change layer or said second phase change layer.
9. The method of claim 8 wherein said no interdiffusion occurs between said fourth phase change layer and said third phase change layer.
10. The method of claim 1 wherein said phase change memory further includes a fourth phase change layer, said current not inducing interdiffusion of said fourth phase change layer with either said first phase change layer or said second phase change layer.
11. The method of claim 10 wherein said current does not induce interdiffusion of said fourth phase change layer with said third phase change layer.