IP Library Granted Patent US 8,699,595
Granted Patent B2
US 8,699,595 · App. 13/322,944 · Granted Apr 15, 2014

Integrated circuit with channel estimation module and method therefor

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Quick Facts
Patent No.
US 8,699,595
App. No.
13/322,944
Granted
Apr 15, 2014
Kind
B2
Abstract

An integrated circuit comprises channel estimation module for generating at least one channel estimation signal based on at least one of a plurality of pilot signals within concurrent resource elements. The channel estimation module comprising extension module arranged to receive a demodulation reference signal comprises the plurality of pilot signals and to add an extension to the demodulation reference signal, inverse discrete Fourier transform (IDFT) module arranged to perform an inverse discrete Fourier transform function on the extended demodulation reference signal to generate a time domain reference signal, reference signal separation module arranged to separate out at least one pilot signal component from the time domain reference signal. The channel estimation module further comprises and discrete Fourier transform (DFT) module arranged to perform a discrete Fourier transform function on the at least one pilot signal component to generate at least one extended channel estimation signal.

Claims (41)

1. An integrated circuit comprising:

a channel estimation circuit to generate at least one channel estimation signal based on at least one of a plurality of pilot signals within concurrent resource elements,

wherein the channel estimation circuit comprises:

an extension circuit to receive a demodulation reference signal comprising the plurality of pilot signals, to add an extension to the demodulation reference signal, to separately extrapolate odd and even streams of the demodulation reference signal to determine respective extensions for separate pilot signals respective to the odd and even streams, and to remix and append the extrapolated odd and even streams to the demodulation reference signal;

an inverse discrete Fourier transform (IDFT) circuit to perform an inverse discrete Fourier transform function on the extended demodulation reference signal to generate a time domain reference signal;

a reference signal separation circuit to separate out at least one pilot signal component from the time domain reference signal; and

a discrete Fourier transform (DFT) circuit to perform a discrete Fourier transform function on the at least one pilot signal component to generate at least one extended channel estimation signal.

2. The integrated circuit of claim 1 wherein the DFT circuit is further to trim at least one edge of the at least one extended channel estimation signal in order to generate the channel estimation signal.

3. The integrated circuit of claim 1 wherein the extension circuit is further to:

determine at least one extension for separate frequency domain signals for the pilot signals individually, and

sum extensions for separate frequency domain signals to generate an overall extension for the demodulation reference signal.

4. The integrated circuit of claim 1 wherein the plurality of pilot signals are based on a known reference symbol multiplied by a known pilot sequence.

5. The integrated circuit of claim 4 wherein the extension circuit is further to multiply the received demodulation reference signal by a conjugate of the pilot sequence prior to said adding the extension to the demodulation reference signal.

6. The integrated circuit of claim 4 wherein the pilot sequence comprises one of a Zadoff-Chu or constant amplitude zero autocorrelation waveform sequence.

7. The integrated circuit of claim 1 wherein the channel estimation circuit further comprises a shift circuit to perform a circular shift function on the at least one pilot signal component separated out from the time domain reference signal to relocate the at least one pilot signal component to a channel tap corresponding to a first sample interval.

8. The integrated circuit of claim 1 wherein the channel estimation circuit further comprises:

a filter circuit to filter the at least one pilot signal component separated out from the time domain reference signal.

9. The integrated circuit of claim 1 wherein the channel estimation circuit is adapted for use within a receiver chain circuit to receive data within an orthogonal frequency division multiplexing (OFDM) communication system.

10. The integrated circuit of claim 1 wherein the channel estimation circuit is adapted for use within a receiver chain circuit to receive data within a multiple input multiple output (MIMO) communication system.

11. A communication unit comprising the integrated circuit of claim 1 .

12. A method for generating a channel estimation signal, the method comprising:

receiving a demodulation reference signal comprising a plurality of pilot signals;

determining respective extensions for separate pilot signals, wherein said determining the respective extensions comprises separately extrapolating odd and even streams respective to the separate pilot signals of the demodulation reference signal;

remixing and appending the extrapolated odd and even streams to the demodulation reference signal to generate an extended demodulation reference signal;

performing an inverse discrete Fourier transform (IDFT) function on the extended demodulation reference signal to generate a time domain reference signal;

separating out at least one pilot signal component from the time domain reference signal; and

performing a discrete Fourier transform (DFT) function on the at least one pilot signal component to generate at least one extended channel estimation signal.

13. The method of claim 12 further comprising:

trimming at least one edge of the at least one extended channel estimation signal to generate the channel estimation signal.

14. The method of claim 12 further comprising:

extending a frequency domain signal of the demodulation reference signal, wherein said extending the frequency domain signal provides one or more of the frequency domain signal is extended to a length of a power of two,

the extended frequency domain signal comprises no discontinuities in a region around a beginning or an end of the original frequency domain signal, and

an extension applied to the beginning of the frequency domain signal and an extension applied to the end of the frequency domain signal start and end respectively at a same amplitude.

15. The method of claim 12 further comprising:

determining at least one extension for separate frequency domain signals for the pilot signals individually; and

generating an overall extension for the demodulation reference signal by summing extensions for separate frequency domain signals.

16. The method of claim 12 further comprising:

performing a circular shift function on the at least one pilot signal component separated out from the time domain reference signal to relocate the at least one pilot signal component to a channel tap corresponding to a first sample interval.

17. The integrated circuit of claim 1 wherein the extension circuit adds the extension to the demodulation reference signal by estimating tangents at a start and an end of a real frequency domain representation of the demodulation reference signal and forming the extension as a curve based on the tangents.

18. The method of claim 12 wherein the adding the extension comprises:

estimating tangents at a start and an end of a real frequency domain representation of the demodulation reference signal.

Assignments (29)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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