IP Library Granted Patent US 8,898,408
Granted Patent B2
US 8,898,408 · App. 13/323,428 · Granted Nov 25, 2014

Memory controller-independent memory mirroring

Inventors: Stuart Allen Berke (Austin, TX); William Sauber (Georgetown, TX)
Assignee: Dell Products L.P.
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Quick Facts
Patent No.
US 8,898,408
App. No.
13/323,428
Filed
Dec 12, 2011
Granted
Nov 25, 2014
Kind
B2
Examiner
DOAN, HAN V
Art Unit
2136
USPC
711/162
Abstract

A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment.

Claims (58)

1. A method of memory controller-independent memory mirroring in an information handling system (IHS), comprising:

providing a mirroring association between a first memory segment and a second memory segment that are located in a system memory and that are coupled to a memory buffer, wherein the mirroring association is independent of a memory controller that is associated with the system memory and the second memory segment is unknown to the memory controller;

receiving, by the memory buffer from the memory controller, write data that is directed to a first memory location in the first memory segment;

writing, independent of the memory controller with the memory buffer, the write data to both the first memory segment and the second memory segment according to the mirroring association such that the first memory segment includes primary write data and the second memory segment includes mirrored write data that is a copy of the primary write data;

receiving, by the memory buffer from the memory controller, a plurality of read commands directed to the first memory location in the first memory segment, and, in response:

retrieving read data by reading the write data from an alternating one of the first memory segment and the second memory segment in response to the plurality of read commands; and

storing the read data in the memory buffer such that the memory buffer includes both first read data that is the primary write data that was read from the first memory segment in response to the plurality of read commands and second read data that is the mirrored write data that was read from the second memory segment in response to the plurality of read commands; and

performing, by the memory controller without knowledge of the mirroring association between the first memory segment and the second memory segment, a patrol scrubbing process using the first read data and the second read data in the memory buffer such that each of a plurality of addresses in both the first memory segment and the second memory segment are subject to the patrol scrubbing process over the plurality of read commands, wherein a patrol scrub rate is set in the memory controller such that each of the plurality of addresses in both the first memory segment and the second memory segment are subject to the patrol scrubbing process over the plurality of read commands within a predetermined amount of time.

2. The method of claim 1 , further comprising:

utilizing the first read data and the second read data in the memory buffer to determine the cause of a system exception associated with one of the plurality of read commands.

3. The method of claim 2 , further comprising:

storing, in the memory buffer, information identifying which of the first memory segment and the second memory segment was read from last and alternating between the first memory segment and the second memory segment based on the information; and

utilizing the information to determine the cause of the system exception.

4. The method of claim 2 , wherein the utilizing the first read data and the second read data includes determining whether one of the first read data and the second read data includes a miscompare.

5. The method of claim 2 , wherein the utilizing the first read data and second read data includes determining whether the system exception was due to one of a channel transmission error and a write error.

6. The method of claim 1 , further including:

comparing, with the memory buffer, the first read data and the second read data; and

in response to determining that the first read data and the second read data do not match, storing the first read data and the second read data in the memory buffer until the first read data and the second read data are used to determine the cause of a system exception associated with one of the plurality of read commands.

7. The method of claim 1 , further comprising:

receiving, by the memory buffer, memory mirroring configuration information that is used to provide the mirroring association.

8. A method of memory controller-independent memory mirroring in an information handling system (IHS), comprising:

receiving, by a memory buffer, memory mirroring configuration information from a management module;

providing, by the memory buffer, a memory mirroring association between a primary memory segment and a secondary memory segment using the memory mirroring configuration information, wherein the memory mirroring association is independent of a memory controller and the second memory segment is unknown to the memory controller;

receiving, by the memory buffer, write commands and write data from the memory controller, wherein the write commands are directed toward addresses in the primary memory segment;

writing the write data to both addresses in the primary memory segment and to addresses in the secondary memory segment independent of the memory controller using the memory buffer such that the primary memory segment includes primary write data at the addresses in the primary memory segment and the secondary memory segment includes mirrored write data at the addresses in the secondary memory segment that is a copy of the primary write data;

receiving, by the memory buffer, a first read command from the memory controller, the first read command being directed toward the addresses in the primary memory segment;

selecting, by the memory buffer in response to the first read command, one of the primary memory segment and the secondary memory segment from which to read the write data according to the first read command, wherein the selecting is independent of the memory controller;

retrieving, by the memory buffer based on the selecting in response to the first read command, first read data that is one of (1) the primary write data from the addresses in the primary memory segment or (2) the secondary write data from the addresses in the secondary memory segment;

caching the first read data in the memory buffer and storing tracking information identifying the selected one of the primary memory segment and the secondary memory segment;

receiving, by the memory buffer, a plurality of subsequent read commands from the memory controller, the plurality of subsequent read commands being directed toward the addresses in the primary memory segment;

selecting, by the memory buffer in response to the plurality of subsequent read commands and using the stored tracking information, the one of the primary memory segment and the secondary memory segment that was not selected according to a previous read command;

retrieving, by the memory buffer based on the selecting in response to the second read command, either the first read data that is the primary write data from the addresses in the primary memory segment, or second read data that is the secondary write data from the addresses in the secondary memory segment that were not selected according to the previous read command;

comparing, by the memory buffer, the first read data and the second read data;

in response to determining that the first read data and the second read data do not match, holding the first read data and the second read data in the memory buffer until the management module can analyze the first read data and the second read data; and

performing, by the memory controller without knowledge of the mirroring association between the first memory segment and the second memory segment, a patrol scrubbing process using the first read data and the second read data in the memory buffer such that each of the addresses in both the first memory segment and the second memory segment are subject to the patrol scrubbing process over the first read command and the plurality of subsequent read commands, wherein a patrol scrub rate is set in the memory controller such that each of the addresses in both the first memory segment and the second memory segment are subject to the patrol scrubbing process over the plurality of read commands within a predetermined amount of time.

9. The method of claim 8 , further comprising:

maintaining, in the memory buffer, a list of addresses in the primary memory segment to which read commands from the memory controller have been directed, wherein the maintaining includes storing tracking information identifying which of the first memory segment and the second memory segment was read from last for each address in the list of addresses.

10. The method of claim 9 , wherein the list of addresses is a first-in-first-out list containing, at any given time, at least a number of addresses equal to the total number of outstanding read commands issued by the memory controller at the given time.

11. The method of claim 8 , further comprising:

receiving a subsequent write command from the memory controller, the subsequent write command being directed toward the addresses in the primary memory segment; and

in response to receiving the subsequent write command, deleting the first read data and the second read data and the tracking information from the memory buffer.

12. The method of claim 8 , wherein the primary memory segment and the secondary memory segment are each one of a rank, a bank, a DRAM chip, a DIMM, and an address range of memory locations.

13. An information handling system (IHS), comprising:

a system memory having a plurality of memory segments;

a memory controller that is coupled to the system memory and that is configured to store data in and retrieve data from the plurality of memory segments;

a memory buffer coupled between the memory controller and the plurality of memory segments, wherein the memory buffer is configured to maintain a mirroring association between a first memory segment and a second memory segment in the plurality of memory segments, wherein the mirroring association is independent of the memory controller and the second memory segment is unknown to the memory controller; and

a management module coupled to the system memory, the memory buffer, and the memory controller, wherein the management module is configured to transmit mirroring association configuration information to the memory buffer;

wherein the memory buffer is further configured to:

receive write data from the memory controller that is directed to memory locations in the first memory segment;

write the write data to both the memory locations in the first memory segment and to memory locations in the second memory segment according to the mirroring association such that the first memory segment includes primary write data and the second memory segment includes mirrored write data that is a copy of the primary write data;

receive a plurality of read commands directed to the memory locations in the first memory segment from the memory controller, and, in response to the plurality of read commands:

retrieve read data by reading the write data from an alternating one of the first memory segment and the second memory segment in response to the plurality of read commands; and

store the read data in the memory buffer such that the memory buffer includes both first read data that is the primary write data that was read from the first memory segment and second read data that is the mirrored write data that was read from the second memory segment; and

wherein the memory controller is configured, without knowledge of the mirroring association between the first memory segment and the second memory segment, to perform a patrol scrubbing process using the first read data and the second read data in the memory buffer such that each of a plurality of addresses in both the first memory segment and the second memory segment are subject to the patrol scrubbing process over the plurality of read commands, and wherein a patrol scrub rate is set in the memory controller such that each of the addresses in both the first memory segment and the second memory segment are subject to the patrol scrubbing process over the plurality of read commands within a predetermined amount of time.

14. The method of claim 13 , wherein the management module is further configured to utilize the first read data and second read data in the buffer to determine the cause of a system exception associated with one of the plurality of read commands.

15. The method of claim 14 , wherein the memory buffer is further configured to store information identifying which of the first memory segment and the second memory segment was read from last and alternate between the first memory segment and the second memory segment based on the information, and wherein the management module is further configured to utilize the information in the buffer to determine the cause of the system exception.

16. The method of claim 13 , wherein the memory buffer is further configured to compare the first read data and the second read data and, if the first read data and the second read data do not match, hold the first read data and the second read data in the memory buffer until the management module can utilize the first read data and the second read data to determine the cause of a system exception associated with one of the plurality of read commands.

17. The method of claim 16 , wherein the management module is further configured to determine whether one of the first read data and the second read data includes an error.

Assignments (15)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2016
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: DELL MARKETING L.P.; ASAP SOFTWARE EXPRESS, INC.; APPASSURE SOFTWARE, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL INC.; DELL PRODUCTS L.P.; DELL USA L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040040/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2016
From: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: DELL MARKETING L.P.; ASAP SOFTWARE EXPRESS, INC.; APPASSURE SOFTWARE, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL INC.; DELL PRODUCTS L.P.; DELL USA L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040065/0618 →
RELEASE OF SECURITY INTEREST Recorded Sep 13, 2016
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: DELL MARKETING L.P.; ASAP SOFTWARE EXPRESS, INC.; APPASSURE SOFTWARE, INC.; COMPELLANT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL INC.; DELL PRODUCTS L.P.; DELL USA L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040065/0216 →
PATENT SECURITY AGREEMENT (ABL) Recorded Jan 2, 2014
From: DELL INC.; APPASSURE SOFTWARE, INC.; ASAP SOFTWARE EXPRESS, INC.; BOOMI, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL USA L.P.; FORCE10 NETWORKS, INC.; GALE TECHNOLOGIES, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 031898/0001 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded Jan 2, 2014
From: DELL INC.; APPASSURE SOFTWARE, INC.; ASAP SOFTWARE EXPRESS, INC.; BOOMI, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL USA L.P.; FORCE10 NETWORKS, INC.; GALE TECHNOLOGIES, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 031899/0261 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Jan 2, 2014
From: APPASSURE SOFTWARE, INC.; ASAP SOFTWARE EXPRESS, INC.; BOOMI, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL INC.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL USA L.P.; FORCE10 NETWORKS, INC.; GALE TECHNOLOGIES, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS FIRST LIEN COLLATERAL AGENT
Reel/Frame 031897/0348 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2011
From: BERKE, STUART ALLEN; SAUBER, WILLIAM
To: DELL PRODUCTS L.P.
Reel/Frame 027368/0442 →
Continuity (1)
Related Publication 20130151767A1 · Jun 13, 2013