Wafer-level packaging with compression-controlled seal ring bonding

1. A method of providing a device in a sealed package, comprising:

aligning a first continuous seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a second continuous seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains a device to be packaged;

forcibly effecting movement of the first and second wafer surfaces toward one another with the first and second seal rings aligned in opposing relationship and thereby compressing the first and second seal rings against one another; and

providing between the first and second wafer surfaces a physical barrier, other than the first and second seal rings, against said movement.

2. The method of claim 1 , wherein said providing a physical barrier includes creating the physical barrier during said movement.

3. The method of claim 2 , wherein said creating includes creating the physical barrier during said compressing.

4. The method of claim 3 , including, during said compressing, stopping said movement with said physical barrier and thereby stopping said compressing.

5. The method of claim 2 , wherein said creating is effected by said movement.

6. The method of claim 1 , including, during said compressing, stopping said movement with said physical barrier and thereby stopping said compressing.

7. The method of claim 1 , wherein said providing a physical barrier includes providing said physical barrier as an integral part of at least one of the wafers.

8. A device packaged according to a process that includes the steps of claim 1 .

9. A method of preparing a semiconductor wafer for use in packaging a device in a sealed package, comprising:

providing on a surface of said wafer a continuous seal ring having a bonding surface generally parallel to and offset from said wafer surface, said bonding surface adapted to contact a cooperating continuous seal ring on another semiconductor wafer during a seal ring bonding operation; and

providing on said wafer, with said seal ring interposed therebetween, first and second stop surfaces generally parallel to said bonding surface and disposed between said bonding surface and said wafer surface, said first and second stop surfaces respectively adapted to contact cooperating stop surfaces on said another wafer while said bonding surface is contacting said another seal ring during said seal ring bonding operation.

10. The method of claim 9 , wherein said providing first and second stop surfaces includes providing on said wafer surface first and second stop structures that respectively define said first and second stop surfaces.

11. The method of claim 9 , wherein said providing first and second stop surfaces includes forming in said wafer a trench having a depth that is less than a height of said seal ring and having a bottom that defines said wafer surface.

12. The method of claim 9 , wherein said providing a seal ring includes providing the seal ring in surrounding relationship to a portion of said wafer that contains said device.

13. A device packaged according to a process that includes the steps of claim 9 .

14. A wafer assembly for use in packaging a device in a sealed package, comprising:

a semiconductor wafer;

a continuous seal ring provided on a surface of said wafer and having a bonding surface generally parallel to and offset from said wafer surface, said bonding surface adapted to contact a cooperating continuous seal ring on another semiconductor wafer during a seal ring bonding operation; and

means defining first and second stop surfaces generally parallel to said bonding surface and disposed between said bonding surface and said wafer surface, said first and second stop surfaces adapted to contact cooperating stop surfaces on said another wafer while said bonding surface is contacting said another seal ring during said seal ring bonding operation, wherein said seal ring is interposed between said first and second stop surfaces.

15. The wafer assembly of claim 14 , wherein said means defining first and second stop surfaces includes first and second stop structures provided on said wafer surface and respectively defining said first and second stop surfaces.

16. The wafer assembly of claim 15 , wherein said first and second stop structures are configured as continuous rings.

17. The wafer assembly of claim 14 , wherein said means defining first and second stop surfaces includes means defining in said wafer a trench having a depth that is less than a height of said seal ring and having a bottom that defines said wafer surface.

18. The wafer assembly of claim 14 , wherein said first and second stop surfaces are generally coplanar surfaces.

19. The wafer assembly of claim 14 , wherein said first and second stop surfaces have approximately equal surface areas.

20. The wafer assembly of claim 14 , wherein said first and second stop surfaces have respectively different surface areas.

21. The wafer assembly of claim 14 , wherein said first and second stop surfaces are approximately equidistant from said seal ring.

22. The wafer assembly of claim 14 , wherein said first and second stop surfaces are located at respectively different distances from said seal ring.

23. The wafer assembly of claim 14 , wherein said seal ring surrounds a portion of said wafer that contains said device.

24. A sealed device package assembly, comprising:

a device provided on a first wafer portion of a first semiconductor wafer and interposed between said first wafer portion and a second wafer portion of a second semiconductor wafer;

a first seal formed between said first and second wafer portions and surrounding a part of said first wafer portion that contains said device; and

a further seal formed between said first and second wafer portions and surrounding said part of said first wafer portion, wherein:

said first seal and said further seal are compressively formed seals and the first seal is a product of more compression than the further seal.

25. The assembly of claim 24 , wherein said first and second wafer portions have been singulated from said first and second wafers, respectively.

26. The assembly of claim 24 , wherein the first seal is a metal seal and the further seal is of a material other than metal.