Optimized data communications in a parallel computer
View Patent ↗A parallel computer includes nodes that include a network adapter that couples the node in a point-to-point network and supports communications in opposite directions of each dimension. Optimized communications include: receiving, by a network adapter of a receiving compute node, a packet—from a source direction—that specifies a destination node and deposit hints. Each hint is associated with a direction within which the packet is to be deposited. If a hint indicates the packet to be deposited in the opposite direction: the adapter delivers the packet to an application on the receiving node; forwards the packet to a next node in the opposite direction if the receiving node is not the destination; and forwards the packet to a node in a direction of a subsequent dimension if the hints indicate that the packet is to be deposited in the direction of the subsequent dimension.
1. An apparatus for optimized data communications in a parallel computer, the parallel computer comprising a plurality of compute nodes, each compute node comprising a network adapter, the network adapters coupling the compute nodes in a multi-dimension point-to-point network for data communications, each network adapter supporting communications in opposite directions of each dimension, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
receiving, by a network adapter of a receiving compute node, a data communications packet from a source direction of a source dimension, the packet specifying a compute node as a destination of the packet and specifying a plurality of deposit hints, each separate deposit hint associated uniquely with a direction of a dimension of the point-to-point network and each deposit hint indicating that the packet is to be deposited at each compute node in the associated direction on a path to the destination compute node;
if a deposit hint indicates that the packet is to be deposited at compute nodes in the opposite direction of the source direction in the source dimension;
delivering, by the network adapter, the packet to an application executing on the receiving compute node;
forwarding the packet to a next compute node in the opposite direction of the source dimension only if the packet does not specify the receiving compute node as the destination of the packet; and
forwarding the packet to a next compute node in a direction of a subsequent dimension only if the deposit hints indicate that the packet is to be deposited at compute nodes in the direction of the subsequent dimension, wherein each deposit hint comprises a binary bit having a value of one in a bit pattern, where all other bits of the bit pattern have a value of zero; wherein forwarding the packet to a next compute node in a direction of a subsequent dimension further comprises identifying the direction of the subsequent dimension by identifying a next bit in the bit pattern to have a value of one and determining the direction and dimension represented by the bit.
2. The apparatus of claim 1 , wherein forwarding the packet to a next compute node in the opposite direction of the source dimension and forwarding the packet to a next compute node in a direction of subsequent dimension are carried out in parallel.
3. The apparatus of claim 1 , wherein delivering, by the network adapter, the packet to an application executing on the receiving compute node further comprises storing, by the network adapter, the packet directly in the application's allocated memory space.
4. The apparatus of claim 1 , wherein delivering, by the network adapter, the packet to an application executing on the receiving compute node further comprises delivering, by the network adapter, to a Direct Memory Access (‘DMA’) engine, the packet, wherein the DMA engine is configured to store the packet through one or more DMA operations in the application's allocated memory space.
5. A computer program product for optimized data communications in a parallel computer, the parallel computer comprising a plurality of compute nodes, each compute node comprising a network adapter, the network adapters coupling the compute nodes in a multi-dimension point-to-point network for data communications, each network adapter supporting communications in opposite directions of each dimension, the computer program product disposed upon a computer readable storage medium, wherein the computer readable storage medium is not a signal, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:
receiving, by a network adapter of a receiving compute node, a data communications packet from a source direction of a source dimension, the packet specifying a compute node as a destination of the packet and specifying a plurality of deposit hints, each separate deposit hint associated uniquely with a direction of a dimension of the point-to-point network and each deposit hint indicating that the packet is to be deposited at each compute node in the associated direction on a path to the destination compute node;
if a deposit hint indicates that the packet is to be deposited at compute nodes in the opposite direction of the source direction in the source dimension;
delivering, by the network adapter, the packet to an application executing on the receiving compute node;
forwarding the packet to a next compute node in the opposite direction of the source dimension only if the packet does not specify the receiving compute node as the destination of the packet; and
forwarding the packet to a next compute node in a direction of a subsequent dimension only if the deposit hints indicate that the packet is to be deposited at compute nodes in the direction of the subsequent dimension, wherein each deposit hint comprises a binary bit having a value of one in a bit pattern, where all other bits of the bit pattern have a value of zero; wherein forwarding the packet to a next compute node in a direction of a subsequent dimension further comprises identifying the direction of the subsequent dimension by identifying a next bit in the bit pattern to have a value of one and determining the direction and dimension represented by the bit.
6. The computer program product of claim 5 , wherein forwarding the packet to a next compute node in the opposite direction of the source dimension and forwarding the packet to a next compute node in a direction of subsequent dimension are carried out in parallel.
7. The computer program product of claim 5 , wherein delivering, by the network adapter, the packet to an application executing on the receiving compute node further comprises storing, by the network adapter, the packet directly in the application's allocated memory space.
8. The computer program product of claim 5 , wherein delivering, by the network adapter, the packet to an application executing on the receiving compute node further comprises delivering, by the network adapter, to a Direct Memory Access (‘DMA’) engine, the packet, wherein the DMA engine is configured to store the packet through one or more DMA operations in the application's allocated memory space.