Methods and apparatus for reduced gate resistance finFET
View Patent ↗Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.
1. A metal gate transistor structure, comprising:
a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart;
a metal containing gate electrode formed over the semiconductor substrate and overlaps a channel gate region of each of the semiconductor fins in a top view;
an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate;
a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; and
a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts;
wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins.
2. The metal gate transistor structure of claim 1 and further comprising:
a high-K gate dielectric disposed between the gate electrode and the semiconductor fins.
3. The metal gate transistor structure of claim 2 , wherein the gate dielectric has a dielectric constant of greater than about 10.
4. The metal gate transistor structure of claim 2 , wherein the gate dielectric is one selected from the group consisting essentially of a nitrogen containing oxide layer, a hafnium containing oxide layer, a tantalum containing oxide layer, or an aluminum containing oxide layer.
5. The metal gate transistor structure of claim 4 , wherein source and drain regions are formed adjacent the channel gate regions for each of the plurality of semiconductor fins and are further coupled together to form a single finFET transistor.
6. The metal gate transistor structure of claim 1 , wherein the gate electrode comprises a metal one selected from the group consisting essentially of aluminum, tantalum, tungsten, molybdenum, and titanium.
7. The metal gate transistor structure of claim 1 , wherein the semiconductor fins further comprise source and drain regions formed adjacent to the channel gate regions.
8. The metal gate transistor structure of claim 1 , wherein the plurality of contacts are each formed over the gate electrode in an area between the semiconductor fins.
9. The metal gate transistor structure of claim 1 , wherein the plurality of contacts are each spaced from the channel gate region of the fins by a minimum spacing distance.
10. The metal gate transistor structure of claim 9 , wherein the minimum spacing distance is at least 8 nanometers.
11. The metal gate transistor of claim 1 , wherein the number of semiconductor fins is greater than about 10.
12. The metal gate transistor of claim 11 , wherein the number of contacts is greater than about 20.
13. An integrated circuit comprising:
at least one circuit formed of a plurality of metal gate transistors, each further comprising:
a plurality of semiconductor fins formed over a semiconductor substrate, the semiconductor fins being arranged in parallel and spaced apart;
a metal containing gate electrode formed over the semiconductor substrate and overlaps a channel gate region of each of the semiconductor fins in a top view; and extending over the semiconductor substrate between the semiconductor fins;
an interlevel dielectric layer overlying the metal containing gate electrode and the semiconductor substrate;
a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the metal containing gate electrode; and
a low resistance metal strap formed over the interlevel dielectric layer and coupled to the metal containing gate electrode by the plurality of contacts.
14. The integrated circuit of claim 13 , wherein the metal containing gate electrode further comprises one selected from the group consisting essentially of aluminum, tantalum, tungsten, molybdenum, and titanium.
15. The integrated circuit of claim 13 , and further comprising a high-K gate dielectric disposed between the metal containing gate electrode and the channel gate region of each of the semiconductor fins.
16. The integrated circuit of claim 13 , wherein for each of the metal gate transistors, the plurality of contacts are each spaced from the channel gate region of the semiconductor fins by a minimum spacing distance.