Configurable flip-flop
View Patent ↗A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal.
1. A device comprising a master-slave flip-flop, the flip-flop comprising:
a master stage;
a slave stage to receive first data propagated from an output of the master stage;
a clock input;
a first flush control input;
a second flush control input;
a data input; and
a data output, the flip-flop configured to:
when a first flush control signal at the first flush control input is in a first state, latch data present at the data input in response to assertion of a clock signal at the clock input;
when the first flush control signal is in a second state, buffer data present at the data input independent of the clock signal at the clock input;
when a second flush control signal at the second flush control input is in a third state, latch data present at the output of the master stage in response to assertion of a clock signal at the clock input; and
when the second flush control signal is in a fourth state, buffer data present at the output of the master stage independent of the clock signal at the clock input.
2. The device of claim 1 , wherein the flip-flop further comprises:
the master stage comprising a master input coupled to the data input, a master output, and a first control input , the master stage configured to latch data at the master stage or buffer data at the master stage based on a first control signal at the first control input; and
a master flush module comprising an input coupled to the first flush control input, an input coupled to the clock input and an output coupled to the first control input to provide the first control signal based on the first flush control signal and the clock signal.
3. The device of claim 1 , wherein the flip-flop is configured to latch data or buffer data at the master stage of the flip-flop based on the first flush control signal and to latch data or buffer data at the slave stage of the flip-flop based on the second flush control signal at the second flush control input.
4. The device of claim 1 , the flip-flop further comprising:
the master stage comprising a master input coupled to the data input, a master output, and a first control input, the master stage configured to latch data at the master stage or buffer data at the master stage based on a first control signal at the first control input; and
a master flush module comprising an input coupled to the first flush control input, an input coupled to the clock input and an output coupled to the first control input to provide the first control signal based on the first flush control signal and the clock signal.
5. The device of claim 4 , wherein the flip-flop further comprises:
the slave stage comprising a slave input coupled to the master output, a slave output coupled to the data output, and a second control input, the slave stage configured to latch data at the slave stage or buffer data at the slave stage based on a second control signal at the second control input; and
a slave flush module comprising an input coupled to the second flush control input, an input coupled to the clock input and an output coupled to the second control input to provide the second control signal based on the second flush control signal and the clock signal.
6. The device of claim 1 , wherein the flip-flop further comprises:
a test input;
a test enable input, the flip-flop configured to selectively couple the data input and the test input to the data output based on a test control signal at the test enable input.
7. The device of claim 1 , further comprising:
a first stage of an instruction pipeline coupled to the data input of the flip-flop; and
a state-retention flip-flop comprising a data output coupled to the first stage of the instruction pipeline.
8. A master-slave flip-flop comprising:
an data input;
a master stage; and
a slave stage to receive first data propagated from an output of the master stage;
the flip-flop configured to, in a first mode of operation, latch data present at the data input at a master stage of the flip-flop based on a clock signal and configured to and buffer data present at the output of the master stage at the slave state of the flip-flop independent of the clock signal, and in a second mode of operation, buffer data at the data input at the master stage independent of the clock signal.
9. The flip-flop of claim 8 , the flip-flop configured to, in the second mode of operation, latch data at the slave stage based on the clock signal.
10. A method, comprising:
in response to determining a master-slave flip-flop is in a first mode of operation, latching data at a master stage of the flip-flop based on a clock signal, the flip-flop including a master stage and a slave stage to receive first data propagated from an output of the master stage;
in response to determining the flip-flop is in a second mode of operation, buffering data at the master stage of the flip-flop independent of the clock signal
in response to determining the flip-flop is in the third mode of operation, buffering data at a slave stage of the flip-flop independent of the clock signal; and
in response to determining the flip-flop is in the fourth mode of operation, latching data at the slave stage based on the clock signal.
11. The method of claim 10 , further comprising:
wherein buffering data at the master stage of the flip-flop comprises buffering data at the flip-flop independent of a test enable signal, the flip-flop configured to be operated in a test mode based on a state of the test enable signal.
12. The method of claim 11 , further comprising selecting a data input of the flip-flop based on the state of the test enable signal.
13. The method of claim 1 , wherein the slave stage is directly connected to the master stage.