IP Library Granted Patent US 8,274,854
Granted Patent B2
US 8,274,854 · App. 13/330,456 · Granted Sep 25, 2012

Semiconductor storage device and method for producing semiconductor storage device

Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,274,854
App. No.
13/330,456
Granted
Sep 25, 2012
Kind
B2
Abstract

A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.

Claims (9)

1. A method for manufacturing a semiconductor storage device, the method comprising:

generating a test control signal based on one of a test command and a test signal;

generating a first control signal for controlling the semiconductor storage device based on the test control signal and a first signal from an input-signal pad;

generating a second control signal for controlling the semiconductor storage device based on a second signal from a control-signal pad; and

testing the semiconductor storage device based on the first control signal and the second control signal to manufacture the semiconductor storage device.

2. The method for producing the semiconductor storage device according to claim 1 , wherein the control-signal pad is at least one of a DQ-mask-signal pad, a clock-signal pad, a chip-enable-signal pad, a write-enable-signal pad, and an output-enable-signal pad.

3. The method for producing the semiconductor storage device according to claim 1 , wherein at least one of a write operation of a data signal and a read operation of the data signal is performed while a portion of a bit sequence of the data signal is masked based on the first signal.

4. The method for producing the semiconductor storage device according to claim 1 , wherein at least one of a clock synchronous test and a clock asynchronous test is performed,

wherein a clock signal is supplied as the first signal in the clock synchronous test and a fixed signal is supplied as the second signal in the asynchronous test.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
CHANGE OF NAME Recorded Dec 29, 2011
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 027464/0533 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2011
From: HARA, KOTA
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 027448/0185 →
Priority Claims (1)
JP 2008-019316 · Jan 30, 2008 · national
Continuity (2)
Division 12360621 · Jan 27, 2009
Related Publication 20120087195A1 · Apr 12, 2012