Digital signal processing for PLC communications having communication frequencies
Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (ADC), and an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form. This input digital signal can be an oversampled digital signal, where the digital signal is oversampled relative to downstream processing (e.g., FFT-based processing). A processing circuit(s) can then be used to decimate the input digital signal according to a decimation rate. A reference signal can be generated by the processing circuit that is responsive to the decimation rate. The processing circuit can also be used to detect a change in a phase difference between the AC and reference signal and to modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.
1. A circuit-based apparatus comprising:
a transceiver circuit configured and arranged to communicate over power distribution lines that carry power using alternating current (AC);
one or more processing circuits configured and arranged to provide
an analog to digital converter module configured to generate an input digital signal from an analog signal that was received at the transceiver circuit;
a decimator module configured to produce, in response to a variable decimation rate, a decimated input digital signal;
a reference signal generator module configured to generate a reference signal having a frequency responsive to the decimation rate; and
a decimation modification module configured and arranged to modify, in response to an indication of change in a phase difference between the reference signal and the AC, the decimation rate to counteract the phase difference.
2. The circuit-based apparatus of claim 1 , wherein the reference signal generator module is configured and arranged to generate the reference signal using a direct digital synthesizer.
3. The circuit-based apparatus of claim 1 , wherein the decimator module is configured and arranged to set the decimation rate to a fixed number of FFT input samples per each period of the AC.
4. The circuit-based apparatus of claim 1 , wherein the decimation modification module is configured and arranged to set the decimation rate to a fixed number of FFT input samples per each transmitted symbol.
5. The circuit-based apparatus of claim 1 , further including a signal processing module configured and arranged to demodulate the decimated input digital signal.
6. The circuit-based apparatus of claim 1 , further including a signal processing module configured and arranged to demodulate the decimated input digital signal according to an orthogonal frequency division multiple access (OFDMA) spectrum allocation technique.
7. The circuit-based apparatus of claim 1 , wherein the one or more processing circuits are further configured and arranged to provide the modules in parallel for multiple channels that have different carrier frequencies.
8. The circuit-based apparatus of claim 1 , wherein the one or more processing circuits are further configured and arranged to provide a derivative module configured and arranged to produce the indication of change in a phase difference between the reference signal and the AC.
9. The circuit-based apparatus of claim 1 , wherein the one or more processing circuits are further configured and arranged to provide a proportional-integral-derivative (PID) controller module and wherein the PID controller module is configured and arranged to produce the indication of change in a phase difference between the reference signal and the AC.
10. The circuit-based apparatus of claim 1 , wherein the one or more processing circuits are further configured and arranged to provide a fixed decimation module that decimates the input digital signal according to a fixed decimation rate.
11. A method comprising:
converting, using an analog-to-digital converter (ADC), an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form;
using a processing circuit to
decimate the input digital signal according to a decimation rate;
generate a reference signal that is responsive to the decimation rate;
detect a change in a phase difference between the AC and reference signal; and
modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.
12. The method of claim 11 , wherein using a processing circuit to decimate the input digital signal includes producing a decimated signal having a sample rate that accounts for frequency changes in carrier channel frequencies that are caused by corresponding changes in a frequency of the AC.
13. The method of claim 11 , wherein using a processing circuit further includes detecting a change in a phase difference by multiplying a decimated input digital signal with the reference signal.
14. The method of claim 11 , wherein using a processing circuit further includes detecting the change in the phase difference by multiplying a decimated input digital signal with the reference signal and applying a filter to an output of the multiplication.
15. The method of claim 11 , wherein using a processing circuit further includes generating the reference signal by setting a frequency of the reference signal to a value that correlates virtual carrier channel frequencies for the frequency of the reference signal with the decimation rate.
16. The method of claim 11 , wherein using a processing circuit further includes demodulating symbols modulated according to one of multi-tone phase shift keyed, and multi-tone frequency shift keyed, and wherein the demodulation uses the decimated input digital signal.
17. The method of claim 11 , wherein using a processing circuit further includes demodulating the decimated input digital signal according to an orthogonal frequency division multiple access (OFDMA) spectrum allocation technique.
18. The method of claim 11 , wherein using a processing circuit further includes modifying the decimation rate to counteract spectral leaking due to a mismatch in an FFT filling time and carrier channel frequencies.