Techniques for reading a memory cell with electrically floating body transistor
View Patent ↗A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.
1. A method for reading a memory cell, the method comprising:
transitioning a first control signal applied to a source region or a drain region of a transistor of the memory cell from a first voltage level to a second voltage level, the memory cell consisting essentially of the transistor, wherein a body region of the transistor is configured to be electrically floating;
transitioning a second control signal applied to a gate of the transistor from a third voltage level to a fourth voltage level, wherein initiation of the second control signal follows initiation of the first control signal, wherein the second control signal comprises a voltage pulse of shorter duration than the first control signal, wherein a difference between the first voltage level and the third voltage level is as small as approximately 0.8 volts, and wherein a difference between the second voltage level and the fourth voltage level is as small as approximately 1.0 volts; and
sensing a read current released by the transistor for reading both logic high and logic low data states from the memory cell in response to the second control signal.
2. The method of claim 1 , comprising determining a data state of the memory cell at least substantially based on the read current.
3. The method of claim 1 , wherein the body region functions as a base of an inherent bipolar transistor.
4. The method of claim 3 , wherein the body region stores a data bit in the form of a charge accumulated in the body region.
5. The method of claim 4 , wherein the transistor delivers the data bit by discharging the body region in response to the second control signal.
6. The method of claim 5 , wherein the second control signal provides a gate-to-source voltage of approximately zero volts.
7. The method of claim 5 , wherein the discharging provides the read current and the read current is proportional to the current gain of the transistor multiplied by the charge.
8. The method of claim 7 , wherein the read current is a current spike.
9. The method of claim 4 , wherein the transistor delivers the data bit by discharging the body region in response to the first control signal.
10. The method of claim 9 , wherein the first control signal provides a drain-to-source voltage in a range of one (1) to 2.2 volts.
11. The method of claim 9 , wherein the discharging provides the read current and the read current is proportional to the current gain of the transistor multiplied by the charge.
12. The method of claim 11 , wherein the read current is a current spike.
13. The method of claim 1 , wherein the gate is disposed over a first portion of the body region.
14. The method of claim 13 , wherein the source region adjoins a second portion of the body region that is adjacent the first portion and separates the source region from the first portion.
15. The method of claim 14 , wherein the drain region adjoins a third portion of the body region that is adjacent the first portion and separates the drain region from the first portion.
16. The method of claim 13 , wherein the third voltage level may cause minority carriers to accumulate in the first portion of the body region.
17. The method of claim 16 , wherein the minority carriers accumulate at a surface region of the first portion of body region that is juxtaposed or near a gate dielectric which is disposed between the gate and the first portion of the body region.
18. The method of claim 16 , wherein a region that includes the minority carriers is disconnected from the source region by the second portion of the body region.
19. The method of claim 16 , wherein a region that includes the minority carriers is disconnected from the drain region by the third portion of the body region.
20. The method of claim 1 , wherein the body region includes a first type of semiconductor material and the source region and drain region include a second type of semiconductor material.
21. The method of claim 20 , wherein the source region includes a lightly doped region.
22. The method of claim 20 , wherein the source region includes a highly doped region.
23. The method of claim 20 , wherein the source region includes a lightly doped region and a highly doped region.
24. The method of claim 20 , wherein the drain region includes a lightly doped region.
25. The method of claim 20 , wherein the drain region includes a highly doped region.
26. The method of claim 20 , wherein the drain region includes a lightly doped region and a highly doped region.
27. A method for reading a memory cell, the method comprising:
coupling a read-source line of data sense circuitry to a source region or a drain region of a transistor of the memory cell, the memory cell consisting essentially of the transistor, wherein a body of the transistor is electrically floating;
coupling a read-word line of the data sense circuitry to a gate of the transistor;
shifting a voltage level of the read-source line from a first voltage level to a second voltage level;
shifting a voltage level of the read-word line from a third voltage level to a fourth voltage level;
sensing a discharge current released by the transistor for reading both logic high and logic low data states from the memory cell in response to the shifting voltage level of the read-word line; and
determining a data state of the memory cell at least substantially based on the discharge current;
wherein a difference between the first voltage level and the third voltage level is as small as approximately 0.8 volts, and wherein a difference between the second voltage level and the fourth voltage level is as small as approximately 1.0 volts.