Method for fabricating semiconductor device by changing work function of gate metal layer

1. A method for fabricating a semiconductor device, comprising:

forming a gate dielectric layer on a substrate;

forming a metal layer including a compound of carbon and nitrogen on the gate dielectric layer;

breaking a bond among carbon, nitrogen and/or metal included in the metal layer through an ion implantation process on the metal layer;

after the breaking of the bond, forming a second silicon layer and a tungsten layer on the metal layer; and

etching the tungsten layer, the second silicon layer, the metal layer and the gate dielectric layer to form a gate.

2. The method of claim 1 , wherein the substrate is a region where an NMOSFET is formed and the gate serves as a gate of the NMOSFET.

3. The method of claim 1 , wherein, after the breaking of the bond, the metal layer has a work function of approximately 3.7 eV to approximately 4.4 eV.

4. The method of claim 1 , wherein the ion implantation process is performed using arsenic (As) or Argon (Ar).

5. The method of claim 1 , wherein the metal electrode includes a tantalum carbon nitride (TaCN) layer.

6. The method of claim 1 , wherein the gate dielectric layer includes a stack structure of a silicon oxide layer and a dielectric layer.

7. The method of claim 6 , wherein the dielectric layer has a higher dielectric constant than the silicon oxide layer.

8. The method of claim 6 , wherein the dielectric layer includes hafnium silicate (HfSiO).

9. The method of claim 1 , further comprising:

forming a first silicon layer on the metal layer before the decreasing of the work function.

10. A method for fabricating a semiconductor device, comprising:

forming a gate dielectric layer on a substrate including a first region and a second region;

forming a metal layer including a compound of carbon and nitrogen on the gate dielectric layer, wherein the metal layer has different work functions in the first region and the second region, respectively; and

etching the metal layer and the gate dielectric layer to form a first gate and a second gate in the first region and the second region, respectively,

wherein a metal electrode formed from the metal layer in the first region has a work function lower than a work function of a metal electrode formed from the metal layer in the second region and a nitrogen concentration of the metal electrode of the first region is smaller than a nitrogen concentration of the metal electrode of the second region,

wherein the first region is a region where an NMOSFET is formed and the first gate serves as a gate of the NMOSFET, and

wherein the second region is a region where a PMOSFET is formed and the second gate serves as a gate of the PMOSFET.

11. The method of claim 10 , wherein the gate dielectric layer includes a stack structure of a silicon oxide layer and a dielectric layer.

12. The method of claim 11 , wherein the dielectric layer includes hafnium silicate (HfSiO).

13. The method of claim 10 , wherein the metal layer includes a TaCN layer.

14. The method of claim 10 , wherein the forming of the metal layer having different work functions comprises:

forming a first metal layer including a compound of carbon and nitrogen on the gate dielectric layer; and

performing an ion implantation process on the first metal layer of the first region.

15. The method of claim 14 , further comprising: forming a silicon layer on metal layers of the first region and the second region.

16. The method of claim 14 , wherein the performing of the ion implantation process is performed using arsenic (As) or Argon (Ar).