Lightly doped silicon carbide wafer and use thereof in high power devices

1. A semiconductor device, comprising:

a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side,

a first contact electrode arranged at the front side of the drift zone,

a control region arranged at the front side and controlling an injection of carriers of at least the first conductivity type into the drift zone, and

a second contact electrode at the backside of the drift zone,

wherein the drift zone is arranged to carry a carrier flow between the first and the second contact electrode, and wherein the drift zone comprises a silicon carbide wafer with a net carrier concentration less than 10 15 cm −3 and a carrier lifetime of at least 50 ns, and wherein the silicon carbide wafer has a surface forming the front side or the back side surface of the drift zone and being off-oriented towards a Miller index direction with an off-axis angle less than 1 degree.

2. The device according to claim 1 , wherein the control region comprises:

at least two base regions of a second conductivity type with a predetermined depth, being arranged at the front side surface within the drift zone and being separated by a space;

a source region of the first conductivity type located at the front side surface and within the base regions of the second conductivity type;

a channel region arranged at the front side surface within the base region comprising the source region and arranged between the source region and an edge of the base region;

a gate electrode for controlling the channel region; and

a gate insulation region for electrically separating the gate electrode from the channel region.

3. The device according to claim 2 , wherein the gate insulation region is located above the channel region with an overlap over the source region and completely overlapping the space between the base regions.

4. The device according to claim 2 , wherein the first electrode is an emitter electrode with an ohmic contact common to the source region and the base region and being electrically isolated from the gate electrode.

5. The device according to claim 1 , wherein the first electrode is an emitter electrode extending over the whole front side of the drift zone.

6. The device according to claim 1 , wherein the second contact electrode is a collector electrode forming a layer arranged on the surface of the backside of the drift zone.

7. The device according to claim 1 , wherein a collector region is located at the backside surface within the drift zone.

8. The device according to claim 7 , wherein the collector region forms an ohmic contact with the second electrode.

9. The device according to claim 7 , wherein the collector region is of a second conductivity type.

10. The device according to claim 7 , wherein the collector region extends over the whole backside of the drift zone and comprises a field stop region.

11. The device according to claim 7 , wherein the collector region is divided into several units spaced by small areas, wherein the second contact electrode forms an ohmic contact common with each collector unit and the drift zone or a field stop region within the drift zone.

12. The device according to claim 1 , wherein the backside of the drift zone comprises a junction termination extension for reverse blocking.

13. The device according to claim 1 , wherein the front side of the drift zone comprises a junction termination extension for forward blocking.

14. The device according to claim 1 , wherein the front side of the drift zone comprises alignment marks in order to align the structures provided on the backside of the drift zone with the structure on the front side.

15. The device according to claim 1 , wherein the device is an IGBT.

16. The device according to claim 1 , wherein the surface of the silicon carbide wafer has an on-axis orientation.