Apparatus having error detection in sequential logic
View Patent ↗According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
1. An apparatus, comprising:
a logic circuit configured to receive an input signal having an input value and to generate an output signal having an output value that corresponds to the input value; and
an error detector having:
a comparator configured to compare the input value to the output value and configured to indicate whether the output value corresponds to the input value; and
an amplifier having a first node configured to receive the input signal and a second node configured to receive the output signal, the amplifier configured to amplify a difference between the input value and the output value.
2. The apparatus of claim 1 wherein the logic circuit includes a sequential logic circuit.
3. The apparatus of claim 1 wherein the logic circuit includes a latch.
4. The apparatus of claim 1 wherein the logic circuit is configured to generate the output signal in response to an edge of a clock signal.
5. The apparatus of claim 1 wherein the logic circuit is configured to generate the output signal having an output value that approximately equals the input value.
6. The apparatus of claim 1 wherein:
the logic circuit is configured to generate the output signal in response to an edge of a clock signal; and
the error detector is configured to indicate that the output value does not correspond to the input value if the input signal transitions to the input value less than a set-up time of the logic circuit before the edge of the clock.
7. The apparatus of claim 1 wherein the amplifier comprises a differential amplifier having a first amplifier node coupled to receive the input signal and a second amplifier node coupled to receive the output signal.
8. The apparatus of claim 1 wherein the amplifier comprises a differential amplifier having a first amplifier node coupled to receive the input signal and a second amplifier node coupled to receive the output signal, the differential amplifier being unbalanced in favor of the first amplifier node.
9. The apparatus of claim 1 wherein:
the amplifier is configured to receive the input signal while a clock has a first level and configured to receive the output signal while the clock has the first level, the amplifier configured to amplify a signal across the first and second amplifier nodes while the clock has a second level; and
the comparator having a first input node coupled to the first amplifier node, having a second input node configured to receive the output signal, and the comparator configured to generate a signal that indicates whether the output value corresponds to the input value.
10. The apparatus of claim 1 wherein:
the amplifier is configured to receive the input signal while a clock has a first level, and configured to receive the output signal while the clock has the first level, the amplifier configured to amplify a signal across the first and second amplifier nodes for a time that is less than a time during which the clock has a second level; and
the comparator having a first input node coupled to the first amplifier node, having a second input node configured to receive the output signal, and the comparator configured to generate a signal that indicates whether the output value corresponds to the input value.
11. The apparatus of claim 1 wherein:
the amplifier is configured to receive the input signal while a clock has a first level and configured to receive the output signal while the clock has the first level, the amplifier configured to amplify a signal across the first and second amplifier nodes while the clock has a second level; and
the error detector further comprises an exclusive-or gate having a first input node coupled to the first amplifier node, having a second input node configured to receive the output signal, and the exclusive-or gate configured to generate a signal that indicates whether the output value corresponds to the input value.
12. The apparatus of claim 1 wherein:
the amplifier is configured to receive the input signal while a clock has a first level, and configured to receive the output signal while the clock has the first level, the amplifier configured to amplify a signal across the first and second amplifier nodes while the clock has a second level; and
the comparator circuit having a first input node coupled to the first amplifier node, having a second input node configured to receive the output signal, a stability detector configured to determine whether a signal on the first amplifier node is stable, and the comparator circuit configured to generate a signal that indicates whether the output value corresponds to the input value.
13. An apparatus, comprising:
a logic circuit configured to receive an input signal having an input value and to generate an output signal having an output value that corresponds to the input value; and
an error detector configured to indicate whether the output value corresponds to the input value;
wherein the error detector includes:
an intermediate node;
a comparator having a first comparator-input node coupled to receive the output signal, having a second comparator-input node, and configured to generate a signal that indicates whether the output value corresponds to the input value;
a differential amplifier having first and second amplifier nodes;
a first switch configured to couple the input signal to the second comparator-input node while a clock signal has a first level and to uncouple the input signal from the second comparator-input node while the clock signal has a second level;
a second switch configured to couple the second comparator-input node to the first amplifier node while the clock signal has the second level and to uncouple the second comparator-input node from the first amplifier node while the clock signal has the first level;
a third switch configured to couple the output signal to the intermediate node while the clock signal has the first level and to uncouple the input signal from the intermediate node while the clock signal has the second level; and
a fourth switch configured to couple the intermediate node to the second amplifier node while the clock signal has the second level and to uncouple the intermediate node from the second amplifier node while the clock signal has the first level.
14. An integrated circuit, comprising:
a logic circuit configured to receive an input signal having an input value and to generate an output signal having an output value that corresponds to the input value; and
an error detector having:
a comparator configured to compare the input value to the output value and configured to indicate whether the output value corresponds to the input value; and
an amplifier having a first node configured to receive the input signal and a second node configured to receive the output signal, the amplifier configured to amplify a difference between the input value and the output value.
15. A system, comprising:
a first integrated circuit, including:
a logic circuit configured to receive an input signal having an input value and to generate an output signal having an output value that corresponds to the input value; and
an error detector having:
a comparator configured to compare the input value to the output value and configured to indicate whether the output value corresponds to the input value; and
an amplifier having a first node configured to receive the input signal and a second node configured to receive the output signal, the amplifier configured to amplify a difference between the input value and the output value; and
a second integrated circuit coupled to the first integrated circuit.
16. The system of claim 15 wherein one of the first and second integrated circuits includes a controller.
17. The system of claim 15 wherein the first and second integrated circuits are disposed on a same die.
18. The system of claim 15 wherein the first and second integrated circuits are disposed on respective dies.
19. A method, comprising:
causing an output signal to have an output value in response to an input signal;
comparing the output signal to the input signal through an imbalanced differential amplifier; and
determining whether the output value corresponds to an input value of the input signal.
20. The method of claim 19 wherein causing the output signal to have the output value includes causing the output signal to have the output value in response to a transition of a clock signal from a clock level to another clock level.
21. The method of claim 19 wherein determining whether the output value corresponds to the input value of the input signal includes determining whether the output value approximately equals the input value.
22. The method of claim 19 wherein determining whether the output value corresponds to the input value of the input signal includes determining whether the output value corresponds to the input value approximately during a time that a clock signal transitions from a clock level to another clock level.
23. The method of claim 19 wherein determining whether the output value corresponds to the input value of the input signal includes:
amplifying the input signal; and
determining whether the output value corresponds to a value of the amplified input signal.
24. The method of claim 19 wherein determining whether the output value corresponds to the input value of the input signal includes:
amplifying a difference between the input signal and a previous output value of the output signal; and
determining whether the output value corresponds to a value of the amplified difference.
25. An apparatus, comprising:
a logic circuit configured to receive an input signal having an input value and to generate an output signal having an output value that corresponds to the input value;
a first switch coupled to receive the input signal and configured to generate a clocked input signal;
a second switch coupled to receive the output signal and configured to generate a clocked output signal; and
a comparator having a first comparator-input node coupled to receive the clocked output signal, having a second comparator-input node coupled to receive the clocked input signal, and configured to generate a signal that indicates whether the output value corresponds to the input value.