Semiconductor device having insulating film with increased tensile stress and manufacturing method thereof

1. A semiconductor device, comprising:

a semiconductor substrate;

a first gate electrode and a second gate electrode each formed over a main surface of the semiconductor substrate and adjacent to each other;

a first sidewall spacer formed over a first side wall of the first gate electrode opposing the second gate electrode;

a second sidewall spacer formed over a second side wall of the second gate electrode opposing the first gate electrode;

a first insulating film comprising silicon and nitrogen formed over the main surface of the semiconductor substrate so as to cover the first and second gate electrodes and the first and second sidewall spacers;

a second insulating film comprising silicon and nitrogen formed over the first insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers; and

a silicon-oxide-based third insulating film formed over the second insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers,

wherein, when a spacing between the first sidewall spacer and the second sidewall spacer is L 0 , a film thickness of the first insulating film is T 1 , a spacing between the first insulating film over a side surface of the first sidewall spacer and the first insulating film over a side surface of the second sidewall spacer is L 1 , and a film thickness of the second insulating film is T 2 , L 0 /2>T 1 and L 1 /2≦T 2 are satisfied, and

wherein a hydrogen content of the first insulating film is lower than a hydrogen content of the second insulating film.

2. A semiconductor device according to claim 1 ,

wherein the hydrogen content of the first insulating film is not more than ⅓ of the hydrogen content of the second insulating film.

3. A semiconductor device according to claim 2 ,

wherein a tensile stress of the first insulating film is larger than a tensile stress of the second insulating film.

4. A semiconductor device according to claim 3 ,

wherein the first insulating film is formed of a laminate film of a plurality of silicon nitride films, and

wherein a hydrogen content of each of the silicon nitride films forming the first insulating film is lower than the hydrogen content of the second insulating film.

5. A semiconductor device according to claim 4 ,

wherein each of the first gate electrode and the second gate electrode is a gate electrode of an n-channel MISFET.

6. A semiconductor device according to claim 5 , further comprising:

a contact hole formed in the third, second, and first insulating films; and

a conductive plug formed in the contact hole.

7. A semiconductor device according to claim 3 ,

wherein the first insulating film comprises a one-layer silicon nitride film.

8. A semiconductor device according to claim 3 , further comprising:

an additional insulating film between the second insulating film and the third insulating film, wherein:

a hydrogen content of the first insulating film is lower than a hydrogen content of the additional insulating film; and

a tensile stress of the first insulating film is greater than a tensile stress of the additional insulating film.

9. A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming a first gate electrode and a second gate electrode adjacent to each other over a main surface of a semiconductor substrate;

(b) forming a first sidewall spacer over a first side wall of the first gate electrode opposing the second gate electrode and forming a second sidewall spacer over a second side wall of the second gate electrode opposing the first gate electrode;

(c) forming a first insulating film comprising silicon and nitrogen over the main surface of the semiconductor substrate so as to cover the first and second gate electrodes and the first and second sidewall spacers;

(d) forming a second insulating film comprising silicon and nitrogen over the first insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers; and

(e) forming a silicon-oxide-based third insulating film over the second insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers,

wherein, when a spacing between the first sidewall spacer and the second sidewall spacer each formed in the step (b) is L 0 , a deposited film thickness of the first insulating film in the step (c) is T 1 , a spacing between the first insulating film over a side surface of the first sidewall spacer and the first insulating film over a side surface of the second sidewall spacer at a stage prior to the formation of the second insulating film in the step (d) is L 1 , and a deposited film thickness of the second insulating film in the step (d) is T 2 , L 0 /2>T 1 and L 1 /2≦T 2 are satisfied,

wherein the first insulating film formed in the step (c) is subjected to a treatment for increasing a tensile stress of the first insulating film, prior to forming the second insulating film in step (d), and

wherein the second insulating film formed in the step (d) is not subjected to a treatment for increasing a tensile stress of the second insulating film, prior to forming the third insulating film in step (e).

10. A method of manufacturing a semiconductor device according to claim 9 ,

wherein the treatment for increasing the tensile stress of the first insulating film is one from the group consisting of: an ultraviolet irradiation treatment, an electron beam irradiation treatment, a microwave irradiation treatment, and a heat treatment.

11. A method of manufacturing a semiconductor device according to claim 10 ,

wherein the treatment for increasing the tensile stress is the ultraviolet irradiation treatment, and

wherein, after formation of the first insulating film in step (c) and prior to formation of the second insulating film in step (d), the first insulating film is subjected to the ultraviolet irradiation treatment; and

wherein, after formation of the second insulating film in step (d) and prior to formation of the third insulating film in step (e), the second insulating film is not subjected to the ultraviolet irradiation treatment.

12. A method of manufacturing a semiconductor device according to claim 11 ,

wherein each of the first gate electrode and the second gate electrode is a gate electrode of an n-channel MISFET.

13. A method of manufacturing a semiconductor device according to claim 12 ,

wherein, after the ultraviolet irradiation treatment, the tensile stress of the first insulating film formed in the step (c) is larger than the tensile stress of the second insulating film formed in the step (d).

14. A method of manufacturing a semiconductor device according to claim 13 ,

wherein, in the step (c), after the first insulating film is deposited by a plasma CVD method, the first insulating film is subjected to the ultraviolet irradiation treatment without being exposed to atmospheric air, and

wherein, in the step (d), after the ultraviolet irradiation treatment of the first insulating film, the second insulating film is deposited by a plasma CVD method without being exposed to the atmospheric air.

15. A method of manufacturing a semiconductor device according to claim 9 , comprising, in step (c), forming the first insulating film by:

(c1) forming a silicon nitride film;

(c2) subjecting the silicon nitride film to a treatment for increasing a tensile stress of the silicon nitride film; and

(c3) repeating steps (c1) and (c2) a plurality of times to thereby form the first insulating film as a laminate film comprising a plurality of silicon nitride films, each of which has been subject to a treatment for increasing a tensile stress thereof.

16. A method of manufacturing a semiconductor device according to claim 9 ,

wherein, in the step (c), the first insulating film is formed by a plasma CVD method, and

wherein, in the step (d), the second insulating film is formed by a plasma CVD method.

17. A method of manufacturing a semiconductor device according to claim 16 ,

wherein, in the step (c), a temperature at which the first insulating film is deposited by the plasma CVD method is not less than 400° C., and

wherein, in the step (d), a temperature at which the second insulating film is deposited by the plasma CVD method is not less than 400° C.

18. A method of manufacturing a semiconductor device according to claim 9 , further comprising the steps of:

(f) after the step (e), forming a contact hole in the third, second, and first insulating films; and

(g) forming a conductive plug in the contact hole.

19. A method of manufacturing a semiconductor device according to claim 9 , wherein:

the first insulating film is formed as a one-layer silicon nitride film,

a hydrogen content of the first insulating film is lower than a hydrogen content of the second insulating film, and

a tensile stress of the first insulating film is greater than a tensile stress of the second insulating film.

20. A method of manufacturing a semiconductor device according to claim 9 , further comprising the steps of:

prior to forming the third insulation film, forming an additional insulating film over the second insulating film, such that:

a hydrogen content of the first insulating film is lower than a hydrogen content of the additional insulating film; and

a tensile stress of the first insulating film is greater than a tensile stress of the additional insulating film.

21. A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming a first gate electrode and a second gate electrode adjacent to each other over a main surface of a semiconductor substrate;

(b) forming a first sidewall spacer over a first side wall of the first gate electrode opposing the second gate electrode and forming a second sidewall spacer over a second side wall of the second gate electrode opposing the first gate electrode;

(c) forming a first insulating film comprising silicon and nitrogen over the main surface of the semiconductor substrate so as to cover the first and second gate electrodes and the first and second sidewall spacers;

(d) forming a second insulating film comprising silicon and nitrogen over the first insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers; and

(e) forming a silicon-oxide-based third insulating film over the second insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers,

wherein, when a spacing between the first sidewall spacer and the second sidewall spacer each formed in the step (b) is L 0 , a deposited film thickness of the first insulating film in the step (c) is T 1 , a spacing between the first insulating film over a side surface of the first sidewall spacer and the first insulating film over a side surface of the second sidewall spacer at a stage previous to the formation of the second insulating film in the step (d) is L 1 , and a deposited film thickness of the second insulating film in the step (d) is T 2 , L 0 /2>T 1 and L 1 /2≦T 2 are satisfied,

wherein the first insulating film formed in the step (c) is subjected to a first treatment for increasing a tensile stress of the first insulating film after deposition of the first insulating film,

wherein the second insulating film formed in the step (d) is subjected to a second treatment for increasing a tensile stress of the second insulating film after deposition of the second insulating film, and

wherein conditions for the first treatment and conditions for the second treatment are different from each other.

22. A method of manufacturing a semiconductor device according to claim 21 ,

wherein the first treatment increases the tensile stress of the first insulating film more than the second treatment increases the tensile stress of the second insulating film.

23. A method of manufacturing a semiconductor device according to claim 22 ,

wherein each of the first treatment and the second treatment is an ultraviolet irradiation treatment, and

wherein an illuminance of ultraviolet light in the second treatment is lower than an illuminance of ultraviolet light in the first treatment.

24. A method of manufacturing a semiconductor device according to claim 21 , comprising, in step (c), forming the first insulating film by:

(c1) forming a silicon nitride film;

(c2) subjecting the silicon nitride film to a treatment for increasing a tensile stress of the silicon nitride film; and

(c3) repeating steps (c1) and (c2) a plurality of times to thereby form the first insulating film as a laminate film comprising a plurality of silicon nitride films, each of which has been subject to a treatment for increasing a tensile stress thereof, and each of which has a tensile stress greater than the tensile stress of the second insulating film.

25. A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming a first gate electrode and a second gate electrode adjacent to each other over a main surface of a semiconductor substrate;

(b) forming a first sidewall spacer over a first side wall of the first gate electrode opposing the second gate electrode and forming a second sidewall spacer over a second side wall of the second gate electrode opposing the first gate electrode;

(c) forming a first insulating film comprising silicon and nitrogen over the main surface of the semiconductor substrate so as to cover the first and second gate electrodes and the first and second sidewall spacers, and then subjecting the first insulating film to a treatment for increasing a tensile stress thereof,

(d) forming a second insulating film comprising silicon and nitrogen over the first insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers; and

(e) forming a silicon-oxide-based third insulating film over the second insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers, without first subjecting the second insulating film to a treatment for increasing a tensile stress of the second insulating film, whereby:

a hydrogen content of the first insulating film is lower than a hydrogen content of the second insulating film; and

a tensile stress of the first insulating film is greater than a tensile stress of the second insulating film.

26. A complementary metal insulator semiconductor field effect transistor (CMISFET) comprising:

an n-channel MISFET comprising:

a first gate electrode and a second gate electrode formed adjacent to each other;

a first sidewall spacer formed over a first side wall of the first gate electrode opposing the second gate electrode;

a second sidewall spacer formed over a second side wall of the second gate electrode opposing the first gate electrode;

a first insulating film comprising silicon and nitrogen formed over the main surface of the semiconductor substrate so as to cover the first and second gate electrodes and the first and second sidewall spacers;

a second insulating film comprising silicon and nitrogen formed over the first insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers; and

a silicon-oxide-based third insulating film formed over the second insulating film so as to cover the first and second gate electrodes and the first and second sidewall spacers,

wherein a hydrogen content of the first insulating film is lower than a hydrogen content of the second insulating film; and

a tensile stress of the first insulating film is greater than a tensile stress of the second insulating film; and

a p-channel MISFET comprising:

a third gate electrode and a fourth gate electrode formed adjacent to each other;

a third sidewall spacer formed over a first side wall of the third gate electrode opposing the fourth gate electrode;

a fourth sidewall spacer formed over a second side wall of the fourth gate electrode opposing the third gate electrode;

a fourth insulating film comprising silicon and nitrogen formed over the main surface of the semiconductor substrate so as to cover the third and fourth gate electrodes and the third and fourth sidewall spacers; and

a silicon-oxide-based fifth insulating film formed over the fourth insulating film so as to cover the third and fourth gate electrodes and the third and fourth sidewall spacers;

wherein:

the fourth insulating film is formed so as to provide compression stress.