IP Library Granted Patent US 8,839,001
Granted Patent B2
US 8,839,001 · App. 13/341,630 · Granted Sep 16, 2014

Infinite key memory transaction unit

Inventors: Edward C. King (Pleasanton, CA); Paul J. Lemmon (Livermore, CA); Laszlo Hars (Lafayette, CO)
Assignee: The Boeing Company
G06F12/1408G06F21/79
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Quick Facts
Patent No.
US 8,839,001
App. No.
13/341,630
Granted
Sep 16, 2014
Kind
B2
Abstract

A system for providing high security for data stored in memories in computer systems is disclosed. A different encryption key is used for every memory location, and a write counter hides rewriting of the same data to a given location. As a result, the data for every read or write transaction between the microprocessor and the memory is encrypted differently for each transaction for each address, thereby providing a high level of security for the data stored.

Claims (35)

1. A method for storing ciphertext data at an address in memory of a computer system, the method comprising:

generating an encryption key as a function of the address and versioning information, the versioning information based on a number of writes to the address:

encrypting plaintext data with the encryption key;

generating an authentication value for the address, the authentication value including a keyed hash value that is based on the versioning information, the plaintext data, a random number, and the address; and

storing the encrypted data, the versioning information, and the authentication value at the address.

2. A method as in claim 1 wherein the authentication value for the address is a function of the versioning information, the plaintext, and an accumulator value based on the random number and the address.

3. A method as in claim 2 wherein the accumulator value is used to compute a key that controls hash logic for generating the authentication value.

4. A method for providing data security in a computer system including memory, the method comprising:

retrieving encrypted data, a write counter (WC) value and an authentication value stored at an address of the memory, the encrypted data being plaintext data that was encrypted with a unique encryption key for the address, the WC value based on the number of writes made to the address, the authentication value based on a sum of the WC value for the address, the plaintext data for the address and an accumulator value based on a random number;

decrypting the retrieved data and checking the retrieved authentication value to determine whether the decrypted data are valid, wherein, checking the authentication value comprises subtracting the sum of the WC value and the unencrypted data from the authentication value; and

if the decrypted data are valid writing new data to the address from which the data was retrieved using a new key for the encryption of the data, the new key based at least on the address, the updated version information and on the number of writes made to that address.

5. A method as in claim 4 wherein the decrypted data are considered valid if the step of subtracting results in a number which matches contents of an earlier computed accumulator value.

6. A method as in claim 5 wherein the accumulator value was computed using a portion of the address to select a random number stored in a memory.

7. A method as in claim 6 wherein the portion of the address is selected by a portion of the address itself.

8. A method as in claim 7 wherein before being used the random number is rotated based on another portion of the address.

9. A method as in claim 8 wherein the accumulator value comprises addition of the memory address to the random number after being rotated.

10. A method for responding to a request for plaintext data by a unit in a computer system comprising:

receiving an address from the requesting unit;

generating a statstistically different encryption key using the address and a write counter (WC) value, the WC value based on a number of writes to the address;

reading encrypted data and a keyed hash value stored at the address;

using the encryption key to decrypt the encrypted and the data,

using the keyed hash value the address, and the WC value to authenticate the decrypted data; and

if the authentication is successful sending the decrypted data to the requesting unit.

11. A method as in claim 10 wherein the address received from the requesting unit is a logical address and the method further comprises:

converting the logical address into a physical address; and

the step of reading the data reads the data from the physical address.

12. A method as in claim 11 wherein the step of generating the encryption key further comprises generating an encryption key using at least the logical address, the physical address, and a random number.

13. A method as in claim 12 wherein if during an initial use read of the memory, if the decrypted data does not have a predetermined content then an anti-tamper mechanism is triggered.

14. A method as in claim 10 wherein the authentication includes comparing the retrieved hash value to a keyed hash value computed from the address and the retrieved WC value to verify that the data being read has not been tampered with.

15. Apparatus for providing security for storing and retrieving data comprising:

a memory having a set of addressable locations; and

a processor for reading data from the memory and writing data to the memory, the processor being configured to store ciphertext data at an address by generating an encryption key based on the address and version information; generating an authentication value as a hash value keyed from the address the plaintext data and the version information encrypting the plaintext data with the encryption key; and storing (i) the encrypted data, (ii) version information and (iii) the authentication value at the address,

wherein the processor modifies the write counter value for each new write operation at the address.

16. Apparatus as in claim 15 wherein when reading data from an address in the memory the processor is further configured to retrieve the encrypted data, the version information and the authentication value stored at the address; decrypt the encrypted data; and use the authentication value and the version information to authenticate the decrypted data.

17. Apparatus as in claim 16 wherein the processor is further configured to, if the decrypted data are valid, write new ciphertext data to the address using a new encryption key generated from the address, and updated version information.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2013
From: CPU TECHNOLOGY, INC.
To: THE BOEING COMPANY
Reel/Frame 030545/0984 →
MERGER Recorded May 9, 2013
From: IONU SECURITY, INC.
To: THE BOEING COMPANY
Reel/Frame 030380/0653 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2012
From: LEMMON, PAUL J.; HARS, LASZLO
To: CPU TECHNOLOGY, INC.
Reel/Frame 029535/0797 →
Continuity (2)
Provisional Application 61505039 · Jul 6, 2011
Related Publication 20130013934A1 · Jan 10, 2013